From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C05D83E3163 for ; Tue, 19 May 2026 08:25:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779179131; cv=none; b=DqP0IMlLchaRbFKhjUiDWI2+6vrgvHcMWEsH4nM6EYa8PQPSuNhXEuf0DFl8BYwQjMOYcewLkiz0sclmZi2hFL3lV7Jqz736WAau5vNZRe78iomZIxfJNf/ewGahHMbcbPLOXbbMbFlr3isK9FP4AY+sSW3oWaMnk/xfaDPkK4I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779179131; c=relaxed/simple; bh=yKScYuuUJS7xZJRRgYdhSorlTkDWtLSZgrLiv6hxvFw=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=bcKE5+YGiZEabJgj/bEbyFDlNjQp9tT/rzcASroqt1pnZDBeySTRitZ0/m0LcffimwliDNntHJt/XwTjsdv5ErutdtqUGzrmvg901kDACxplJnwDyDTmvX314GzlE5+X7jempRWNF9Z1bkLSh49Ta84lQy1zi2f9/byh+89d2zU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=Ew1EM6je; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="Ew1EM6je" Received: from killaraus.ideasonboard.com (unknown [IPv6:2a01:cb1d:8f2:800:42d6:38fa:3bdf:70df]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id F3B6797F; Tue, 19 May 2026 10:25:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1779179115; bh=yKScYuuUJS7xZJRRgYdhSorlTkDWtLSZgrLiv6hxvFw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Ew1EM6jePLOZoXy6YhFq5m77ZX/aS9JzSp8f8++IIR18M4ChpvY692tVYuHAzCqEd ljBbt8YnaPo2zrvvABSe7S5+Gaz/slCnRTSp7Eu4Ajla19YLjrzqOjqvnKTTvRsnNN jnlqRkBSdm8d2JNzZH4QesDZXW3KzMBnngFeT6OE= Date: Tue, 19 May 2026 10:25:26 +0200 From: Laurent Pinchart To: Radhey Shyam Pandey Cc: vkoul@kernel.org, neil.armstrong@linaro.org, michal.simek@amd.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, git@amd.com, Tomi Valkeinen Subject: Re: [PATCH 0/3] phy: zynqmp: fix SERDES scrambler register handling and enable for USB Message-ID: <20260519082526.GB16205@killaraus.ideasonboard.com> References: <20260511163135.2924642-1-radhey.shyam.pandey@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20260511163135.2924642-1-radhey.shyam.pandey@amd.com> Hi Radhey, I haven't really been involved with the phy-zynqmp driver for a while, despite still being listed as a maintainer. I have just sent a patch (you're on CC) to hand maintainership duties over to Tomi Valkeinen, who took over maintainership of the ZynqMP DPSUB driver. As Tomi isn't really involved with the PHYs, in particular with the non-DP PHYs supported by the driver, it could also make more sense for someone from AMD to take over maintainer duties for phy-zynqmp. On Mon, May 11, 2026 at 10:01:32PM +0530, Radhey Shyam Pandey wrote: > This series fixes three related issues in the ZynqMP SERDES PHY > scrambler/encoder bypass path: > > 1. The L0_TM_DISABLE_SCRAMBLE_ENCODER mask incorrectly included bit 2 > of L0_TX_DIG_61, which is a reserved read-only field. Correct the > mask to (BIT(3) | GENMASK(1, 0)). > > 2. xpsgtr_bypass_scrambler_8b10b() used xpsgtr_write_phy() which > performs a full register write, clobbering unrelated bits. Switch > to xpsgtr_clr_set_phy() with clr=mask, set=mask to preserve other > register fields. > > 3. USB Gen1 requires PHY-side scrambling and 8b/10b encoding as > mandated by the USB 3.x specification. The driver was incorrectly > bypassing these for USB, the same as SATA and SGMII where encoding > is handled in the controller. > > Nava kishore Manne (3): > phy: zynqmp: fix L0_TM_DISABLE_SCRAMBLE_ENCODER mask > phy: zynqmp: use read-modify-write for SERDES scrambler bypass > phy: zynqmp: keep SERDES scrambler and 8b/10b enabled for USB > > drivers/phy/xilinx/phy-zynqmp.c | 37 ++++++++++++++++++++++++++------- > 1 file changed, 30 insertions(+), 7 deletions(-) > > > base-commit: 5d6919055dec134de3c40167a490f33c74c12581 -- Regards, Laurent Pinchart