From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F6683F788A for ; Tue, 19 May 2026 09:02:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779181328; cv=none; b=Kw3dECnOfqrZj+1u93kLBygKSicV6awzP3Z0Uh87hPgFc7hjF8565H+C+bDegek0kPYgyFKTS2WJIK8KUdSHfs+VSpVB81ozcWCRvBffOnebEo42tZNl/AF4sz3OBQijUh69lRUYHznnkGu6+NmIxf4jHSRmIbpoBwUCgjefmJY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779181328; c=relaxed/simple; bh=t4dc/uQKHAV33hkQ7VeDETtoUrrUhDgC2o3bONeq+AU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XvEQWWfgJwsEl91nxJcQJ2TTTx0B2Krj0XayMXhSV/O7+k2RkDrrEgVv1PlDIcQGg+W5PvZ1jQHe0OzPvMVN6AvVgOPB0yL7xKU7DbF6usVaWPDe25ekcevskglSIXR1WqhmhcmxOZnyVFxfZ0DgwN1roCHAA/mOft1yh+LtCjw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=xfMhTF6E; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="xfMhTF6E" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1779181326; x=1810717326; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=t4dc/uQKHAV33hkQ7VeDETtoUrrUhDgC2o3bONeq+AU=; b=xfMhTF6Emb1HQAD3oWxen0qsJm6yoG+jzVVtDERBl9zcwQn5K+laJTQJ DbPr9IyyTy1KafPxNDyRAn0AX1RfUVjcgWVTBIjb5qYWozDz13x7LUNEc Jyg539dLT6EIhRrGnBdXzg2/uJsG5mfRvgtInAa1qTwzCOFf+BPSoubix TjPZq6ChBILxU0p5bELnvlJldCMsVwg28apiOO9Rp17bqVCYHVZA43oaj OUFrOfGPI1OlDzpgUn+AxNMOjER7wSj2shTWbWmi2D/hvUKRXGWXKyNng VlwFLNcJ/Plyag6IM3nmMD46N8l5/PJ2qV0wlNnyvNGBijm95Tv6K19sf A==; X-CSE-ConnectionGUID: mYWIWAQ5SfKk/NCNR6kc+Q== X-CSE-MsgGUID: VMn+Al8yR2qab3sd17nVOQ== X-IronPort-AV: E=Sophos;i="6.23,243,1770620400"; d="scan'208";a="224955538" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 19 May 2026 02:02:06 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 19 May 2026 02:02:06 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 19 May 2026 02:02:01 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , CC: , Ryan Wanner Subject: [PATCH 2/8] drm: atmel-hlcdc: reorder timing register writes after clock setup Date: Tue, 19 May 2026 14:31:29 +0530 Message-ID: <20260519090135.1188405-3-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260519090135.1188405-1-manikandan.m@microchip.com> References: <20260519090135.1188405-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain From: Ryan Wanner Write CFG(1-4) timing registers after CFG(0) clock configuration rather than before, as required by the datasheet procedure. Signed-off-by: Ryan Wanner Signed-off-by: Manikandan Muralidharan --- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 43 ++++++++++--------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index 7932d666e9ec..9673fbce42a7 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -104,26 +104,6 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) if (ret) return; - vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay; - vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end; - vm.vsync_len = adj->crtc_vsync_end - adj->crtc_vsync_start; - vm.hfront_porch = adj->crtc_hsync_start - adj->crtc_hdisplay; - vm.hback_porch = adj->crtc_htotal - adj->crtc_hsync_end; - vm.hsync_len = adj->crtc_hsync_end - adj->crtc_hsync_start; - - regmap_write(regmap, ATMEL_HLCDC_CFG(1), - (vm.hsync_len - 1) | ((vm.vsync_len - 1) << 16)); - - regmap_write(regmap, ATMEL_HLCDC_CFG(2), - (vm.vfront_porch - 1) | ((vm.vback_porch - 1) << 16)); - - regmap_write(regmap, ATMEL_HLCDC_CFG(3), - (vm.hfront_porch - 1) | ((vm.hback_porch - 1) << 16)); - - regmap_write(regmap, ATMEL_HLCDC_CFG(4), - (adj->crtc_hdisplay - 1) | - ((adj->crtc_vdisplay - 1) << 16)); - prate = clk_get_rate(crtc->dc->hlcdc->sys_clk); mode_rate = adj->crtc_clock * 1000; if (!crtc->dc->desc->fixed_clksrc) { @@ -164,6 +144,29 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) regmap_update_bits(regmap, ATMEL_HLCDC_CFG(0), mask, cfg); + vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay; + vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end; + vm.vsync_len = adj->crtc_vsync_end - adj->crtc_vsync_start; + vm.hfront_porch = adj->crtc_hsync_start - adj->crtc_hdisplay; + vm.hback_porch = adj->crtc_htotal - adj->crtc_hsync_end; + vm.hsync_len = adj->crtc_hsync_end - adj->crtc_hsync_start; + + regmap_write(regmap, ATMEL_HLCDC_CFG(1), + (vm.hsync_len - 1) | + ((vm.vsync_len - 1) << 16)); + + regmap_write(regmap, ATMEL_HLCDC_CFG(2), + (vm.vfront_porch - 1) | + ((vm.vback_porch - 1) << 16)); + + regmap_write(regmap, ATMEL_HLCDC_CFG(3), + (vm.hfront_porch - 1) | + ((vm.hback_porch - 1) << 16)); + + regmap_write(regmap, ATMEL_HLCDC_CFG(4), + (adj->crtc_hdisplay - 1) | + ((adj->crtc_vdisplay - 1) << 16)); + state = drm_crtc_state_to_atmel_hlcdc_crtc_state(c->state); cfg = state->output_mode << 8; -- 2.25.1