From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E5DD24028C8 for ; Tue, 19 May 2026 15:48:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779205730; cv=none; b=rXcEFt+eedlCV9OO74D1HVmatht9wbU+dYr6pGv9JdqzCaIqDPt9JJtxsWMhn2whgkI791I2uSQWt7biUCft5+jl8aH+it21WfKo7VQMCKLQ73LTCS/CDuPhOCvvj54pC/CAkSKWCTfuySmN5iOXUfVtWF6IjNg9omVvHPEGgJQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779205730; c=relaxed/simple; bh=8EnwiIfgwlN2Y7BNtdTxzvy00l8ApsOSgyW1urhamks=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tLdobYw8KXOhIdib4W1EWm32JxBsgEPsPedBwhJMOU6nixZw4S5CJ3DhlBM1rRZFerYU1D6PS6D+Om9dryYFmmkEyuVXgD1aTmpkYO0KxvHrKP7vz5CMd4KyGKRXfNbujGtAmx/JVDgQbMYEDG7jszlCfh9302vSe/MtEXgT3Bo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Wv4x2ia6; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Wv4x2ia6" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 504FE1682; Tue, 19 May 2026 08:48:43 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6A1833F632; Tue, 19 May 2026 08:48:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1779205728; bh=8EnwiIfgwlN2Y7BNtdTxzvy00l8ApsOSgyW1urhamks=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Wv4x2ia68y0kVL6KB2NaaSUj9dVSCqIoOooV5iS2IEugZuZrnmzz5nHQ98e9Uiq2c oK2v1vxo40z4VIGMQ7IFYGocngZ84SjFtUhndmV6u85xfvmHULCXXIAwtENCCeb6U9 R120SQbLTU/URq3Wo5zSVcpY6OF2UDcfw+TlFzw0= From: Yeoreum Yun To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, jie.gan@oss.qualcomm.com, Yeoreum Yun Subject: [PATCH v7 12/13] coresight: etm3x: fix inconsistencies with sysfs configuration Date: Tue, 19 May 2026 16:48:11 +0100 Message-Id: <20260519154812.254884-13-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260519154812.254884-1-yeoreum.yun@arm.com> References: <20260519154812.254884-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The current ETM3x configuration via sysfs can lead to the following inconsistencies: - If a configuration is modified via sysfs while a perf session is active, the running configuration may differ between before a sched-out and after a subsequent sched-in. To resolve these issues, separate the configuration into: - active_config: the configuration applied to the current session - config: the configuration set via sysfs Additionally: - Since active_config and related fields are accessed only by the local CPU in etm_enable/disable_sysfs_smp_call() (similar to perf enable/disable), remove the lock/unlock from the sysfs enable/disable path and starting/dying_cpu path except when to access config fields only. Fixes: 1925a470ce69 ("coresight: etm3x: splitting struct etm_drvdata") Signed-off-by: Yeoreum Yun --- drivers/hwtracing/coresight/coresight-etm.h | 2 + .../coresight/coresight-etm3x-core.c | 38 +++++++++---------- 2 files changed, 21 insertions(+), 19 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index 932bec82fb47..01f1a7f2559c 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -243,6 +243,7 @@ struct etm_config { * @boot_enable:true if we should start tracing at boot time. * @os_unlock: true if access to management registers is allowed. * @traceid: value of the current ID for this component. + * @active_config: structure holding current running configuration parameters. * @config: structure holding configuration parameters. */ struct etm_drvdata { @@ -258,6 +259,7 @@ struct etm_drvdata { bool boot_enable; bool os_unlock; u32 traceid; + struct etm_config active_config; struct etm_config config; }; diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index ccfde9eda537..ed27e35b42ec 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -309,7 +309,7 @@ static int etm_parse_event_config(struct etm_drvdata *drvdata, struct perf_event *event) { const struct etm_caps *caps = &drvdata->caps; - struct etm_config *config = &drvdata->config; + struct etm_config *config = &drvdata->active_config; struct perf_event_attr *attr = &event->attr; u8 ts_level; @@ -368,7 +368,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) int i, rc; u32 etmcr; const struct etm_caps *caps = &drvdata->caps; - struct etm_config *config = &drvdata->config; + struct etm_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev; CS_UNLOCK(drvdata->csa.base); @@ -443,24 +443,30 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) struct etm_enable_arg { struct etm_drvdata *drvdata; struct coresight_path *path; + struct etm_config config; int rc; }; static void etm_enable_sysfs_smp_call(void *info) { struct etm_enable_arg *arg = info; + struct etm_drvdata *drvdata; struct coresight_device *csdev; if (WARN_ON(!arg)) return; - csdev = arg->drvdata->csdev; + drvdata = arg->drvdata; + csdev = drvdata->csdev; if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) { /* Someone is already using the tracer */ arg->rc = -EBUSY; return; } + drvdata->active_config = arg->config; + drvdata->traceid = arg->path->trace_id; + arg->rc = etm_enable_hw(arg->drvdata); /* The tracer didn't start */ @@ -469,6 +475,7 @@ static void etm_enable_sysfs_smp_call(void *info) return; } + drvdata->sticky_enable = true; csdev->path = arg->path; } @@ -513,10 +520,6 @@ static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_pat struct etm_enable_arg arg = { }; int ret; - raw_spin_lock(&drvdata->spinlock); - - drvdata->traceid = path->trace_id; - /* * Configure the ETM only if the CPU is online. If it isn't online * hw configuration will take place on the local CPU during bring up. @@ -524,23 +527,24 @@ static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_pat if (cpu_online(drvdata->cpu)) { arg.drvdata = drvdata; arg.path = path; + + raw_spin_lock(&drvdata->spinlock); + arg.config = drvdata->config; + raw_spin_unlock(&drvdata->spinlock); + ret = smp_call_function_single(drvdata->cpu, etm_enable_sysfs_smp_call, &arg, 1); if (!ret) ret = arg.rc; - if (!ret) - drvdata->sticky_enable = true; } else { ret = -ENODEV; } - if (ret) - etm_release_trace_id(drvdata); - - raw_spin_unlock(&drvdata->spinlock); - if (!ret) dev_dbg(&csdev->dev, "ETM tracing enabled\n"); + else + etm_release_trace_id(drvdata); + return ret; } @@ -567,7 +571,7 @@ static void etm_disable_hw(struct etm_drvdata *drvdata) { int i; const struct etm_caps *caps = &drvdata->caps; - struct etm_config *config = &drvdata->config; + struct etm_config *config = &drvdata->active_config; struct coresight_device *csdev = drvdata->csdev; CS_UNLOCK(drvdata->csa.base); @@ -633,8 +637,6 @@ static void etm_disable_sysfs(struct coresight_device *csdev) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - raw_spin_lock(&drvdata->spinlock); - /* * Executing etm_disable_hw on the cpu whose ETM is being disabled * ensures that register writes occur when cpu is powered. @@ -642,8 +644,6 @@ static void etm_disable_sysfs(struct coresight_device *csdev) smp_call_function_single(drvdata->cpu, etm_disable_sysfs_smp_call, drvdata, 1); - raw_spin_unlock(&drvdata->spinlock); - /* * we only release trace IDs when resetting sysfs. * This permits sysfs users to read the trace ID after the trace -- LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}