From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E3C143546D2 for ; Tue, 19 May 2026 15:48:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779205707; cv=none; b=lypigRyIxBBK4RghfAD7sV0gZVd/r2uV9AF4pO+XxTl1v6T+Uu0uzb+EITpOdGrMLakfrSwwGD0JY2T6X9adJnuB579LUFOMvlhopXDSzdyTveWsWsMtkj6EiOlH4FBiSsv/EM/2DvZqfM6yDR0+XkXpSbCRq26X97UndAOkoYM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779205707; c=relaxed/simple; bh=R8TqSvxEdtBwfrKxIo4gN/zriFxD7ndmTmUy3uLuH/c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=krpOSC1/wEWr/j6kGlWV9ZbbjWepNYFfjnLhdMvJ0KwtAy487ZVdQ5OXj0ZS+tvlKddN7lsYoHAnPG6yk38IAUqGRtgQMxFHTWgRfjtOYNTSfa8TC6kNsqIgSA/eGG2vkCFVQ4M8oGRjNZ3M0SXhc3iZv1ZJOcKIzhmah+wDtwA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=u8jQBVn4; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="u8jQBVn4" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1FFDA244C; Tue, 19 May 2026 08:48:20 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 241A23F632; Tue, 19 May 2026 08:48:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1779205705; bh=R8TqSvxEdtBwfrKxIo4gN/zriFxD7ndmTmUy3uLuH/c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=u8jQBVn4+46nL849BkXPYfv8wn1qoUgz7xQkLuLJ1Vnzpv/6e8ghZTuXbbd+vxvV4 s7q2noaTJGKZ0sob7AlNsHiynYqdOkmQhiGTrZs+GyIuZu1LLYwNTY7rrBsDThj34U /1GlcJghktVPLsy7Fdaw1nJCZAgSYnJLfyEOwMwk= From: Yeoreum Yun To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, jie.gan@oss.qualcomm.com, Yeoreum Yun Subject: [PATCH v7 03/13] coresight: etm4x: introduce ETM_MAX_SEQ_TRANSITIONS Date: Tue, 19 May 2026 16:48:02 +0100 Message-Id: <20260519154812.254884-4-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260519154812.254884-1-yeoreum.yun@arm.com> References: <20260519154812.254884-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit According to IHI006H Embedded Trace Macrocell Architecture Specification [0], n could be 0-2 for TCRSEQEVR when TCRIDR5.NUMSEQSTATE is 0b100. Therefore, introduce ETM_MAX_SEQ_TRANSITIONS macro and apply this in TCRSEQEVR relevant fields. Link: https://developer.arm.com/documentation/ihi0064/latest/ [0] Suggestedby: Leo Yan Signed-off-by: Yeoreum Yun --- drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x.h | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c index c302072b293a..e1a59b434505 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c @@ -76,7 +76,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata, } else if ((offset & GENMASK(11, 4)) == TRCSEQEVRn(0)) { /* sequencer state control registers */ idx = (offset & GENMASK(3, 0)) / 4; - if (idx < ETM_MAX_SEQ_STATES) { + if (idx < ETM_MAX_SEQ_TRANSITIONS) { reg_csdev->driver_regval = &drvcfg->seq_ctrl[idx]; err = 0; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 89d81ce4e04e..60e08ab085c5 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -614,6 +614,7 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx) #define ETM_MAX_NR_PE 8 #define ETMv4_MAX_CNTR 4 #define ETM_MAX_SEQ_STATES 4 +#define ETM_MAX_SEQ_TRANSITIONS (ETM_MAX_SEQ_STATES - 1) #define ETM_MAX_EXT_INP_SEL 4 #define ETM_MAX_EXT_INP 256 #define ETM_MAX_EXT_OUT 4 @@ -877,7 +878,7 @@ struct etmv4_config { u32 vipcssctlr; u8 seq_idx; u8 syncfreq; - u32 seq_ctrl[ETM_MAX_SEQ_STATES]; + u32 seq_ctrl[ETM_MAX_SEQ_TRANSITIONS]; u32 seq_rst; u32 seq_state; u8 cntr_idx; @@ -928,7 +929,7 @@ struct etmv4_save_state { u32 trcvissctlr; u32 trcvipcssctlr; - u32 trcseqevr[ETM_MAX_SEQ_STATES]; + u32 trcseqevr[ETM_MAX_SEQ_TRANSITIONS]; u32 trcseqrstevr; u32 trcseqstr; u32 trcextinselr; -- LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}