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Signed-off-by: Rob Clark Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 1 + drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 20 ++++++++++++++++++++ 3 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 30df9bfa9ef8..a329d20033d7 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2921,6 +2921,7 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs = { .progress = a8xx_progress, .sysprof_setup = a6xx_gmu_sysprof_setup, .perfcntr_configure = a6xx_perfcntr_configure, + .perfcntr_flush = a8xx_perfcntr_flush, }, .init = a6xx_gpu_init, .get_timestamp = a8xx_gmu_get_timestamp, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 99c3e55f5ca8..3491a24a9320 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -334,5 +334,6 @@ void a8xx_preempt_hw_init(struct msm_gpu *gpu); void a8xx_preempt_trigger(struct msm_gpu *gpu); void a8xx_preempt_irq(struct msm_gpu *gpu); bool a8xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring); +void a8xx_perfcntr_flush(struct msm_gpu *gpu); void a8xx_recover(struct msm_gpu *gpu); #endif /* __A6XX_GPU_H__ */ diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index 124d315b2469..6c040f718176 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -1345,3 +1345,23 @@ bool a8xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { return true; } + +void a8xx_perfcntr_flush(struct msm_gpu *gpu) +{ + u32 val; + + /* + * Flush delta counters (both perf counters and pipe stats) present in + * RBBM_S and RBBM_US to perf RAM logic to get the latest data. + */ + gpu_write(gpu, REG_A8XX_RBBM_PERFCTR_FLUSH_HOST_CMD, BIT(0)); + gpu_write(gpu, REG_A8XX_RBBM_SLICE_PERFCTR_FLUSH_HOST_CMD, BIT(0)); + + /* Ensure all writes are posted before polling status register */ + wmb(); + + if (gpu_poll_timeout(gpu, REG_A8XX_RBBM_PERFCTR_FLUSH_HOST_STATUS, val, + val & BIT(0), 100, 100 * 1000)) { + dev_err(&gpu->pdev->dev, "Perfcounter flush timed out: status=0x%08x\n", val); + } +} -- 2.54.0