From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 424EC3F23D1 for ; Wed, 20 May 2026 16:25:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779294349; cv=none; b=uRmwjNxGY1c6abw+GJvJN36AzVTGHdOFxOY5dbTia/qFGtI2WrdKop3v1EfFNUzCd44IRtGM39xyZtJ/lYSJWahwp1Da9QL1+TvCVpzx6nlqQI5bYA4UkYD6Ara578Ybu02zgg1IV+c85vqBMfd5QwhWourOnSQrj2ViYhgFxJA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779294349; c=relaxed/simple; bh=tWIhJ8B+5EdOwL5hDRI/KDJJpq6VqXfLT36CQrcR/bg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=N0jw0hmhZ4xaVE/DPjKjo7BeADVuVQmslbOEROA12/qk90dllGPC4X0khJor8lCfuwlc0itpaKzEOXh5+G0pMJNi3pYsMCpBQnZH+eMH5nMxRyaNOh/uIFPAdZ7ZtAK+yDJm3DemPmkcCFU4n8OUEeNjAL1qCSCta5krgyDay3M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=cMfwhwjR; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=NjEylkrp; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="cMfwhwjR"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="NjEylkrp" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 64KDuZg93680433 for ; Wed, 20 May 2026 16:25:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=eQpOa6u5peh EXhgKaP9zGHIawzycu5fhkque6ul5cd8=; b=cMfwhwjRkFIzTCngjoAnymda0Gr sAoBfkm0HJbsaUbondGJvFfKNb4isg5rDuy57U2KtaliDP4XkvorUYj7fdQERptA mRgRaXdgBqa43cUS6OxjciKaPJucXPC1x7YeNjULOkpRvflVM6A9x2Pf3k1snUR1 OqTh3Y4XDIfGrptAxiD697Rqm4QyhtAg3LY5RoDVAvQIxzwHFDX7709vO9Hu8Ngv ti5eC2IUIcSC9sgTF4gXmVCPO1NJiLXBn0Sr2eqx1ucvCsquZANL9j5UkqglYyPV 5+CbTN2fSYs3pM4ySDv9VZN95M5oIRw2n3c7ItSXEMoJydODKTGEFa7astg== Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e9e9j0p8s-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 20 May 2026 16:25:46 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-365fc4636bbso11077467a91.2 for ; Wed, 20 May 2026 09:25:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1779294346; x=1779899146; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eQpOa6u5pehEXhgKaP9zGHIawzycu5fhkque6ul5cd8=; b=NjEylkrpXZLO9JanIIN5IjWBWBRjTrVbK9Ox4j1If0SWF/aLlocBWUwp60b+Gd8J4t J+QRd4mQ3i3fC+eCp0LRwkwAOjIqLQ2bZrrOAAVol59DoFHNN54T78+TZpxdtMvCdhkR njsA+nPcQeE2KzZbnmaGe8akgSMKVHf9645bC6zWL8TQ/ZrybSuo2WKQc3tHplrL7Yec 5pRY1eQBd48Fa1OqsnM2j5R564UULDyvsyMz3g0Z07gAct1lmlULzEP+lCpbOvPcab1g oqFvaTRBg7zGcLZjA/Ovcig2fH4Q3ilBcuHSx87zRvrZnMtb3j5OnJwhvwK3sP+5jVrw KoHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779294346; x=1779899146; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=eQpOa6u5pehEXhgKaP9zGHIawzycu5fhkque6ul5cd8=; b=JoytQ0pfq+GVzB0XJTmMzS3MBoZWT7WdEnw+vwHIrjAx9xBNwnOahbibb56o7S8IBs HoJF/6TF+PpK+bSBXnp5Hy8/AOypvxglM18S7UupVsBGP7dEJh36Xy26B5bdzm+iBTfQ 4YFD2qeGip/yRSR9OcSMbONQKJjJBgE9OGqV/nKV4qQDWCHrspLUHx/ST13vIXmHmnQG Bmbyc8NmVzMr9Cg0EYRVTha7zG/244EPfeytrRYF0fu7JaUKHWjyaBp49MW4hWMMk4dk LIgGYEV9e/ArHOdpEK4/bg1ZrSk9B87qgLH4GZO84MBLQZYSL/E1kN53i/z/IbqX5ftq Of5w== X-Forwarded-Encrypted: i=1; AFNElJ9UK5grCDSV+VyZdHroUFtB3i96TniE7fOYFXW9vRNhvJB2W217mw0+m5mXpUjy1ISMWhxZx9YsKY5B/gs=@vger.kernel.org X-Gm-Message-State: AOJu0YzzRFPieTvHmtYSLKGwPmo6vH/n5c64jQr9JthbkbOhkO2nZPib o6X6CJKso196jrJsE8W7VhYmdwUin9TwPBaX1EfqgjEViOL/9G6VCJ3n++WMuaDJ+enk0yZI8Hl RXYmfQ4cMHO+F8a7sZcGviRr40TsjldUTV6AiXoN/IRu6Y5kdPjCuM2pBYbekGrJ6W5o= X-Gm-Gg: Acq92OHLsBoR9dvKm6xO3yYZgJRHyG6SGNPGvofNJENQjfgiqZgaD3g2wKCmch9l3yx tdIMCKcb0jLzesLVEqVHlvHoA8lV1597G9lx7WCyXUSNlGyrc5BqiqsQH1tuRavj4Yody5GjVNF LreuAVhHHX989AbK19PcQj5kN/9/S1mH6KdcJWV3kFtWnO9aHZvgrXXNB/T9zGTCY+6RXXd7EKr QyPhOrB0JUouch6gkulPCcKPBzarXDX4QM6BZur54M0VArumoqPrADnOo3UeFbGueRpdV57LJna fZPiyA+ltvpQiygdFflcuixOYblLhW0EZ30TkUeMsimEUVL2Bg4MhbLqjuBmH+lz4D++JsJuEes QJAfl3XZR0KUDf4RhlHEpiXabj46kcz8WSLqbnG69g10= X-Received: by 2002:a17:90b:56cf:b0:369:a74b:28cc with SMTP id 98e67ed59e1d1-369a75a769dmr17241195a91.18.1779294345485; Wed, 20 May 2026 09:25:45 -0700 (PDT) X-Received: by 2002:a17:90b:56cf:b0:369:a74b:28cc with SMTP id 98e67ed59e1d1-369a75a769dmr17241183a91.18.1779294345021; Wed, 20 May 2026 09:25:45 -0700 (PDT) Received: from localhost ([2601:1c0:5000:d5c:4ec8:83f5:8254:6891]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-369703bcc91sm7801065a91.3.2026.05.20.09.25.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2026 09:25:44 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Akhil P Oommen , Rob Clark , Anna Maniscalco , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v8 15/16] drm/msm/a6xx: Append SEL regs to dyn pwrup reglist Date: Wed, 20 May 2026 09:24:02 -0700 Message-ID: <20260520162454.18391-16-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260520162454.18391-1-robin.clark@oss.qualcomm.com> References: <20260520162454.18391-1-robin.clark@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=bfhbluPB c=1 sm=1 tr=0 ts=6a0de08a cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=xqWC_Br6kY4A:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=pGLkceISAAAA:8 a=gjKahejJLxXXi_JFjLAA:9 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: Tc0fLn_sduaID9RgTGIqFWFy9FiZXWAC X-Proofpoint-ORIG-GUID: Tc0fLn_sduaID9RgTGIqFWFy9FiZXWAC X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1OSBTYWx0ZWRfXxpqNujG1aWFH Wb4Qrdmc86rH4+DcW+ZfWXlqCBEpSmtRV5RCcSXJ6MSZj2O39S0bvCXNpRP1ulMFXAuCMCiHWQH Ji/4fIa64xsQ3xU9wcr+9Kg6m6WCxKWbA+Qpzosbg719hewuQvqJQPSGX4pi8eDLB6wZJ3awLd+ o2fBOydEjQPnO3bwlUnqfCpUQOvShs5uTyFsrX13IPk5JD4SShcHn60GM4PfXKudRPrxx6snNmB ICy088FvV6u18gynJtCrS0NXliOrF4GCfT9bom21B5R6z4mEdDhjYUJuub6AFFK3bzw+bCKusK6 884YQLpoyJTUMyzTwzM3jTDG8LpXtPjO96XhHbncyKeqwNSxsY/eU4sAKnKBS2YcOXQCOZdbR9f vaWkRFzDR+9lGYjPqmdMjCq2BfQ79iZ4hBlKAKU1jO30mZnYn3d87IWRqf0QxCYODwlCE+uTSK6 yCFmUdtihcD+p3KQm+g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 adultscore=0 spamscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200159 This is needed so that SEL reg values are restored on exit from IFPC. Signed-off-by: Rob Clark Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 82 +++++++++++++++++++++++++-- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 11 +++- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 1 + 3 files changed, 87 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 61c6b0e781ce..c697a4bdf203 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -946,6 +946,7 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) A7XX_CP_APERTURE_CNTL_HOST_PIPE(PIPE_NONE)); } lock->dynamic_list_len = dyn_pwrup_reglist_count; + a6xx_gpu->dynamic_sel_reglist_offset = dyn_pwrup_reglist_count; } static int a7xx_preempt_start(struct msm_gpu *gpu) @@ -2535,11 +2536,60 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return progress; } +static void +perfcntr_select(struct msm_ringbuffer *ring, enum adreno_pipe pipe, + uint32_t regidx, uint32_t *countables, uint32_t nr, + uint32_t **reglist) +{ + OUT_PKT4(ring, regidx, nr); + for (unsigned i = 0; i < nr; i++) + OUT_RING(ring, countables[i]); + + if (!*reglist) + return; + + for (unsigned i = 0; i < nr; i++) { + /* + * Bitfield is in same position on a7xx, but only 2 bits.. + * which is sufficient for NONE/BR/BV: + */ + *(*reglist)++ = A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe); + *(*reglist)++ = regidx + i; + *(*reglist)++ = countables[i]; + } +} + static void a6xx_perfcntr_configure(struct msm_gpu *gpu, struct msm_ringbuffer *ring, const struct msm_perfcntr_stream *stream) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); enum adreno_pipe pipe = PIPE_NONE; + uint32_t *reglist = NULL; + uint32_t *reglist_sel_start; + + if (to_adreno_gpu(gpu)->info->family >= ADRENO_7XX_GEN1) { + WARN_ON(!a6xx_gpu->pwrup_reglist_emitted); + + struct cpu_gpu_lock *lock = a6xx_gpu->pwrup_reglist_ptr; + int off = (2 * lock->ifpc_list_len) + + (2 * lock->preemption_list_len) + + (3 * a6xx_gpu->dynamic_sel_reglist_offset); + + reglist = (uint32_t *)&lock->regs[0]; + reglist += off; + reglist_sel_start = reglist; + + /* Clear any previously configured SEL reg entries: */ + lock->dynamic_list_len = a6xx_gpu->dynamic_sel_reglist_offset; + + /* + * Ensure CP sees the dynamic_list_len update before we + * start modifying the SEL entries: + */ + dma_wmb(); + } for (unsigned i = 0; i < stream->nr_groups; i++) { unsigned group_idx = msm_perfcntr_group_idx(stream, i); @@ -2567,17 +2617,15 @@ a6xx_perfcntr_configure(struct msm_gpu *gpu, struct msm_ringbuffer *ring, const struct msm_perfcntr_counter *counter = &group->counters[base]; unsigned nr = group_state->allocated_counters; - OUT_PKT4(ring, counter->select_reg, nr); - for (unsigned c = 0; c < nr; c++) - OUT_RING(ring, group_state->countables[c]); + perfcntr_select(ring, pipe, counter->select_reg, + group_state->countables, nr, ®list); for (unsigned s = 0; s < ARRAY_SIZE(counter->slice_select_regs); s++) { if (!counter->slice_select_regs[s]) break; - OUT_PKT4(ring, counter->slice_select_regs[s], nr); - for (unsigned c = 0; c < nr; c++) - OUT_RING(ring, group_state->countables[c]); + perfcntr_select(ring, pipe, counter->slice_select_regs[s], + group_state->countables, nr, ®list); } } @@ -2591,6 +2639,28 @@ a6xx_perfcntr_configure(struct msm_gpu *gpu, struct msm_ringbuffer *ring, OUT_RING(ring, upper_32_bits(rbmemptr(ring, perfcntr_fence))); OUT_RING(ring, stream->sel_fence); + /* + * Update the pwrup reglist size before flushing. Kgsl does a shared- + * memory spinlock dance with SQE to avoid racing with IFPC exit. But + * we can skip that since the ringbuffer programming will be executed + * by SQE after dynamic reglist size is updated. So even if we lose + * the race, the register programming in the rb will overwrite/correct + * the SEL regs restored by SQE on IFPC exit, before sampling begins. + */ + if (reglist) { + struct cpu_gpu_lock *lock = a6xx_gpu->pwrup_reglist_ptr; + unsigned nr_regs = (reglist - reglist_sel_start) / 3; + + /* + * Ensure CP sees updates to the pwrup_reglist before it + * sees the new (increased) length: + */ + dma_wmb(); + + /* Update dynamic reglist len to include new SEL reg programming: */ + lock->dynamic_list_len = a6xx_gpu->dynamic_sel_reglist_offset + nr_regs; + } + a6xx_flush_yield(gpu, ring); /* Check to see if we need to start preemption */ diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 3491a24a9320..f3cc9478b079 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -21,17 +21,19 @@ struct cpu_gpu_lock { uint32_t cpu_req; uint32_t turn; union { + /* a6xx: */ struct { uint16_t list_length; uint16_t list_offset; }; + /* a7xx+: */ struct { uint8_t ifpc_list_len; uint8_t preemption_list_len; uint16_t dynamic_list_len; }; }; - uint64_t regs[62]; + uint64_t regs[]; }; /** @@ -100,6 +102,13 @@ struct a6xx_gpu { uint64_t pwrup_reglist_iova; bool pwrup_reglist_emitted; + /* + * Offset of start of SEL regs appended to pwrup_reglist. This + * is equal to lock->dynamic_list_len if no SEL regs are appended + * to the end of the dynamic reglist. + */ + uint16_t dynamic_sel_reglist_offset; + bool has_whereami; void __iomem *llc_mmio; diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index 6c040f718176..2ce7c6ac4521 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -468,6 +468,7 @@ static void a8xx_patch_pwrup_reglist(struct msm_gpu *gpu) } lock->dynamic_list_len = dyn_pwrup_reglist_count; + a6xx_gpu->dynamic_sel_reglist_offset = dyn_pwrup_reglist_count; done: a8xx_aperture_clear(gpu); -- 2.54.0