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Wed, 20 May 2026 09:25:29 -0700 (PDT) Received: from localhost ([2601:1c0:5000:d5c:4ec8:83f5:8254:6891]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f19c5c020sm21739290b3a.30.2026.05.20.09.25.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2026 09:25:29 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Akhil P Oommen , Rob Clark , Anna Maniscalco , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v8 07/16] drm/msm: Add sysprof accessors Date: Wed, 20 May 2026 09:23:54 -0700 Message-ID: <20260520162454.18391-8-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260520162454.18391-1-robin.clark@oss.qualcomm.com> References: <20260520162454.18391-1-robin.clark@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: l8yZzNwzWPLYAdTrwS1ItDbyMm6EsU3R X-Proofpoint-ORIG-GUID: l8yZzNwzWPLYAdTrwS1ItDbyMm6EsU3R X-Authority-Analysis: v=2.4 cv=UuJT8ewB c=1 sm=1 tr=0 ts=6a0de07b cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=xqWC_Br6kY4A:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=pGLkceISAAAA:8 a=v4b4B-quZFKF0PxyZCUA:9 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1OSBTYWx0ZWRfX2vjJtOE4BQEb PcEhKzPphBgLV8VN2Kam+/cjkyJ9j5lQHZuvYx4uVMmMnd7YvbqT9VIvVpaXpyHIwH++45XeTQE QewGR1GUUFoK3QI31YvuiNV6qDT+/n10EFpvBss4P6hBqBguao+l1pE4KUMZ6AEn4CCdpj1BLiU K/do1uN6vRzwNqIYHOX0fVBNtMEQ7nhjGTf0wINilVc6qnVrkKxLcCMfR3tkVeEdpI2RjVrSMZX HYG0KLoyOePGEChg9L8ySFAPUyCnPS5Grf9aP5uXYWZ4VxOujElkS6FYs5bQ0bRWBDK5/FCw5xu s7GRyg4FWpjSv4XGRMRuMv9+j4kMB1ptV6SM2tTlnTrtxRMIUvAoU7jpqzlXvoL+8keqjNBTSbI QgCbCjSpFQBnpl8k0qdUvBr6ZwI/VgMSLSCtgyFWY8kOxuCrUAJS2bssSHl+ab3r9gqMlFgTag3 R1qyQoSqRSAtDLoL3Qw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 priorityscore=1501 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200159 Currently the sysprof param serves two functions, (a) disabling perfcntr clearing on context switch/preemption, and (b) disabling IFPC. In the future, with kernel side global perfcntr collection/stream, the decision about disabling IFPC will change. To prepare for this, split out two helpers/accessors for the two different cases. For now, they are the same thing, but this will change. Signed-off-by: Rob Clark Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 +++----- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 +++-- drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 2 +- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a8xx_preempt.c | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 18 ++++++++++++++++++ 6 files changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 1b44b9e21ad8..aba08fb76249 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -2036,10 +2036,10 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu) { + bool sysprof = msm_gpu_sysprof_no_ifpc(gpu); struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu = &a6xx_gpu->gmu; - unsigned int sysprof_active; /* Nothing to do if GPU is suspended. We will handle this during GMU resume */ if (!pm_runtime_get_if_active(&gpu->pdev->dev)) @@ -2047,15 +2047,13 @@ void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu) mutex_lock(&gmu->lock); - sysprof_active = refcount_read(&gpu->sysprof_active); - /* * 'Perfcounter select' register values are lost during IFPC collapse. To avoid that, * use the currently unused perfcounter oob vote to block IFPC when sysprof is active */ - if ((sysprof_active > 1) && !test_and_set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) + if (sysprof && !test_and_set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); - else if ((sysprof_active == 1) && test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) + else if (!sysprof && test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) a6xx_gmu_clear_oob(gmu, GMU_OOB_PERFCOUNTER_SET); mutex_unlock(&gmu->lock); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 727281fbef36..71f54ab5425d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -203,7 +203,7 @@ static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, struct msm_ringbuffer *ring, struct msm_gem_submit *submit) { - bool sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; + bool sysprof = msm_gpu_sysprof_no_perfcntr_zap(&a6xx_gpu->base.base); struct msm_context *ctx = submit->queue->ctx; struct drm_gpuvm *vm = msm_context_vm(submit->dev, ctx); struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; @@ -1608,7 +1608,7 @@ static int hw_init(struct msm_gpu *gpu) a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); } - if (!ret && (refcount_read(&gpu->sysprof_active) > 1)) { + if (!ret && msm_gpu_sysprof_no_ifpc(gpu)) { ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); if (!ret) set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status); @@ -2854,6 +2854,7 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs = { .create_private_vm = a6xx_create_private_vm, .get_rptr = a6xx_get_rptr, .progress = a8xx_progress, + .sysprof_setup = a6xx_gmu_sysprof_setup, }, .init = a6xx_gpu_init, .get_timestamp = a8xx_gmu_get_timestamp, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c index df4cbf42e9a4..1e599d4ddea1 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c @@ -261,7 +261,7 @@ void a6xx_preempt_trigger(struct msm_gpu *gpu) mod_timer(&a6xx_gpu->preempt_timer, jiffies + msecs_to_jiffies(10000)); /* Enable or disable postamble as needed */ - sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; + sysprof = msm_gpu_sysprof_no_perfcntr_zap(gpu); if (!sysprof && !a6xx_gpu->postamble_enabled) preempt_prepare_postamble(a6xx_gpu); diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index ccfccc45133f..e022c9a162a4 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -849,7 +849,7 @@ static int hw_init(struct msm_gpu *gpu) */ a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); - if (!ret && (refcount_read(&gpu->sysprof_active) > 1)) { + if (!ret && msm_gpu_sysprof_no_perfcntr_zap(gpu)) { ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); if (!ret) set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status); diff --git a/drivers/gpu/drm/msm/adreno/a8xx_preempt.c b/drivers/gpu/drm/msm/adreno/a8xx_preempt.c index 3d8c33ba722e..6cb53a071801 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_preempt.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_preempt.c @@ -242,7 +242,7 @@ void a8xx_preempt_trigger(struct msm_gpu *gpu) mod_timer(&a6xx_gpu->preempt_timer, jiffies + msecs_to_jiffies(10000)); /* Enable or disable postamble as needed */ - sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; + sysprof = msm_gpu_sysprof_no_perfcntr_zap(gpu); if (!sysprof && !a6xx_gpu->postamble_enabled) preempt_prepare_postamble(a6xx_gpu); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 8c08dc065372..9e5c753437c2 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -311,6 +311,24 @@ static inline bool msm_gpu_active(struct msm_gpu *gpu) return false; } +static inline bool +msm_gpu_sysprof_no_perfcntr_zap(struct msm_gpu *gpu) +{ + return refcount_read(&gpu->sysprof_active) > 1; +} + +static inline bool +msm_gpu_sysprof_no_ifpc(struct msm_gpu *gpu) +{ + /* + * For now, this is the same condition as disabling perfcntr clears + * on context switch. But once kernel perfcntr IFPC support is in + * place, we will only need to disable IFPC for legacy userspace + * setting SYSPROF param. + */ + return msm_gpu_sysprof_no_perfcntr_zap(gpu); +} + /* * The number of priority levels provided by drm gpu scheduler. The * DRM_SCHED_PRIORITY_KERNEL priority level is treated specially in some -- 2.54.0