From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65BD53F4DD7; Wed, 20 May 2026 17:58:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779299892; cv=none; b=BR+NlHyy/7cweEFjlSwv7+Nrl5N80WXpv7Mhz4oiHWEPVtC3cMJO/e5MnnWSwYaE85BFflF0gSJviBcdbcjxPbu8NMPtBAuyShsqnfdmg3p8xKUWeiGxAXW/wKStJWFHQRTMMuMsRW7wxHN3P/cBDgukscyIcfBHLbL0AIx+BAE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779299892; c=relaxed/simple; bh=uMsv9LNQ6VHteVIpcvNZgbtwRtD4fWQkuov8UaIRSgU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oXUWA712duPBmR/u7pE3qQoBlAdSt5mT60XM/3K8iYk4E+0/ekF+Faw59S/sZ50I77uLmnw4kAmr+1Pqqp+MYcZcUbwACDDoiHc0sFDxEDuCL7pAylRd/e9al2xkySYb3Kwd9OltxeOp7burwhEUiHBSFCtNZpyJRxhgFZiWCaI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=KQ1F2OH9; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="KQ1F2OH9" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 3063F277D0; Wed, 20 May 2026 19:58:08 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id hr0zX8cNg0_O; Wed, 20 May 2026 19:58:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1779299887; bh=uMsv9LNQ6VHteVIpcvNZgbtwRtD4fWQkuov8UaIRSgU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=KQ1F2OH9n10E8RJAmX7tgcXuPFB5rgZhEChZx1VvFDt7yvrLzVOXyCqm0PDzdTK91 XHr1KzyaIx4njldjBV+G74g6DOnFWOpVRvu9azsTOEdCx1+sLHH6IexQLLad8mrguI WwxoiilNBUAvDLp6v8rkt+sDJYpoHJchG3OXrDqzwnVe1CW5plLI5QcRIz85L45lYE 3K3Rpc4Co+7utjVD5bUFkECkpLsoUCHTN+est2rqQhRQVbzskiWnZ0zGu+VacKulvo G2QcMrQkZAONvWlWPMivdlPXsHXUVDrGp8jWb9O3FYokKIbgUtbGKYFZST6h4l0y5w P9tF1Oq+7MMUw== From: Rustam Adilov To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanley Chang , Philipp Zabel , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rustam Adilov , Michael Zavertkin Subject: [PATCH v6 2/6] phy: realtek: usb2: introduce read and write functions to driver data Date: Wed, 20 May 2026 22:57:24 +0500 Message-ID: <20260520175728.720877-3-adilov@disroot.org> In-Reply-To: <20260520175728.720877-1-adilov@disroot.org> References: <20260520175728.720877-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit RTL9607C is a big endian SoC with little endian USB host controller but vstatus register is from big endian memory region and thus existing writel doesn't work. It needs either __raw_writel or iowrite32be instead. To handle this situation, introduce read and write function to the driver data and create a default variation for the current RTD SoCs. Assign the existing phy configuration for RTD SoCs to the default read and write function. Co-developed-by: Michael Zavertkin Signed-off-by: Michael Zavertkin Signed-off-by: Rustam Adilov --- drivers/phy/realtek/phy-rtk-usb2.c | 40 ++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-rtk-usb2.c index bd9ee895b9f9..a9e29d2f7e6f 100644 --- a/drivers/phy/realtek/phy-rtk-usb2.c +++ b/drivers/phy/realtek/phy-rtk-usb2.c @@ -67,6 +67,9 @@ struct phy_reg { int vstatus_offset; u32 vstatus_busy; u32 new_reg_req; + + u32 (*read)(void __iomem *reg); + void (*write)(u32 val, void __iomem *reg); }; struct phy_data { @@ -102,6 +105,9 @@ struct phy_cfg { int vstatus_offset; u32 vstatus_busy; u32 new_reg_req; + + u32 (*read)(void __iomem *reg); + void (*write)(u32 val, void __iomem *reg); }; struct phy_parameter { @@ -128,6 +134,16 @@ struct rtk_phy { struct dentry *debug_dir; }; +static u32 rtk_usb2phy_read(void __iomem *reg) +{ + return readl(reg); +} + +static void rtk_usb2phy_write(u32 val, void __iomem *reg) +{ + writel(val, reg); +} + /* mapping 0xE0 to 0 ... 0xE7 to 7, 0xF0 to 8 ,,, 0xF7 to 15 */ static inline int page_addr_to_array_index(u8 addr) { @@ -200,8 +216,8 @@ static int rtk_phy_write(struct phy_reg *phy_reg, char addr, char data) int ret = 0; /* write data to VStatusOut2 (data output to phy) */ - writel((u32)data << shift_bits, - reg_wrap_vstatus + phy_reg->vstatus_offset); + phy_reg->write((u32)data << shift_bits, + reg_wrap_vstatus + phy_reg->vstatus_offset); ret = utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) @@ -985,6 +1001,8 @@ static int parse_phy_data(struct rtk_phy *rtk_phy) phy_parameter->phy_reg.vstatus_offset = phy_cfg->vstatus_offset; phy_parameter->phy_reg.vstatus_busy = phy_cfg->vstatus_busy; phy_parameter->phy_reg.new_reg_req = phy_cfg->new_reg_req; + phy_parameter->phy_reg.read = phy_cfg->read; + phy_parameter->phy_reg.write = phy_cfg->write; if (of_property_read_bool(np, "realtek,inverse-hstx-sync-clock")) phy_parameter->inverse_hstx_sync_clock = true; @@ -1099,6 +1117,8 @@ static const struct phy_cfg rtd1295_phy_cfg = { .vstatus_offset = 0, .vstatus_busy = PHY_VSTS_BUSY, .new_reg_req = PHY_NEW_REG_REQ, + .read = rtk_usb2phy_read, + .write = rtk_usb2phy_write, }; static const struct phy_cfg rtd1395_phy_cfg = { @@ -1126,6 +1146,8 @@ static const struct phy_cfg rtd1395_phy_cfg = { .vstatus_offset = 0, .vstatus_busy = PHY_VSTS_BUSY, .new_reg_req = PHY_NEW_REG_REQ, + .read = rtk_usb2phy_read, + .write = rtk_usb2phy_write, }; static const struct phy_cfg rtd1395_phy_cfg_2port = { @@ -1153,6 +1175,8 @@ static const struct phy_cfg rtd1395_phy_cfg_2port = { .vstatus_offset = 0, .vstatus_busy = PHY_VSTS_BUSY, .new_reg_req = PHY_NEW_REG_REQ, + .read = rtk_usb2phy_read, + .write = rtk_usb2phy_write, }; static const struct phy_cfg rtd1619_phy_cfg = { @@ -1178,6 +1202,8 @@ static const struct phy_cfg rtd1619_phy_cfg = { .vstatus_offset = 0, .vstatus_busy = PHY_VSTS_BUSY, .new_reg_req = PHY_NEW_REG_REQ, + .read = rtk_usb2phy_read, + .write = rtk_usb2phy_write, }; static const struct phy_cfg rtd1319_phy_cfg = { @@ -1207,6 +1233,8 @@ static const struct phy_cfg rtd1319_phy_cfg = { .vstatus_offset = 0, .vstatus_busy = PHY_VSTS_BUSY, .new_reg_req = PHY_NEW_REG_REQ, + .read = rtk_usb2phy_read, + .write = rtk_usb2phy_write, }; static const struct phy_cfg rtd1312c_phy_cfg = { @@ -1235,6 +1263,8 @@ static const struct phy_cfg rtd1312c_phy_cfg = { .vstatus_offset = 0, .vstatus_busy = PHY_VSTS_BUSY, .new_reg_req = PHY_NEW_REG_REQ, + .read = rtk_usb2phy_read, + .write = rtk_usb2phy_write, }; static const struct phy_cfg rtd1619b_phy_cfg = { @@ -1263,6 +1293,8 @@ static const struct phy_cfg rtd1619b_phy_cfg = { .vstatus_offset = 0, .vstatus_busy = PHY_VSTS_BUSY, .new_reg_req = PHY_NEW_REG_REQ, + .read = rtk_usb2phy_read, + .write = rtk_usb2phy_write, }; static const struct phy_cfg rtd1319d_phy_cfg = { @@ -1291,6 +1323,8 @@ static const struct phy_cfg rtd1319d_phy_cfg = { .vstatus_offset = 0, .vstatus_busy = PHY_VSTS_BUSY, .new_reg_req = PHY_NEW_REG_REQ, + .read = rtk_usb2phy_read, + .write = rtk_usb2phy_write, }; static const struct phy_cfg rtd1315e_phy_cfg = { @@ -1320,6 +1354,8 @@ static const struct phy_cfg rtd1315e_phy_cfg = { .vstatus_offset = 0, .vstatus_busy = PHY_VSTS_BUSY, .new_reg_req = PHY_NEW_REG_REQ, + .read = rtk_usb2phy_read, + .write = rtk_usb2phy_write, }; static const struct of_device_id usbphy_rtk_dt_match[] = { -- 2.54.0