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Add reg_addr and reg_index_addr convenience macros for zero-index and indexed access respectively. Extend cs_off_attribute with a u32 index field and update cti_read_single_reg() and cti_write_single_reg() to accept separate offset and index parameters, allowing sysfs show/store handlers to use the attribute's index field directly. Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-core.c | 45 ++++++++++++++--------- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 25 +++++++------ drivers/hwtracing/coresight/coresight-cti.h | 9 +++-- drivers/hwtracing/coresight/coresight-priv.h | 4 +- 4 files changed, 50 insertions(+), 33 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c index 4e7d12bd2d3e..c5cc2706e241 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -42,6 +42,15 @@ static DEFINE_MUTEX(ect_mutex); #define csdev_to_cti_drvdata(csdev) \ dev_get_drvdata(csdev->dev.parent) +static void __iomem *__reg_addr(struct cti_drvdata *drvdata, u32 off, + u32 index) +{ + return drvdata->base + off + sizeof(u32) * index; +} + +#define reg_addr(drvdata, off) __reg_addr((drvdata), (off), 0) +#define reg_index_addr(drvdata, off, i) __reg_addr((drvdata), (off), (i)) + /* write set of regs to hardware - call with spinlock claimed */ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) { @@ -55,16 +64,17 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) /* write the CTI trigger registers */ for (i = 0; i < config->nr_trig_max; i++) { - writel_relaxed(config->ctiinen[i], drvdata->base + CTIINEN(i)); + writel_relaxed(config->ctiinen[i], + reg_index_addr(drvdata, CTIINEN, i)); writel_relaxed(config->ctiouten[i], - drvdata->base + CTIOUTEN(i)); + reg_index_addr(drvdata, CTIOUTEN, i)); } /* other regs */ - writel_relaxed(config->ctigate, drvdata->base + CTIGATE); + writel_relaxed(config->ctigate, reg_addr(drvdata, CTIGATE)); if (config->asicctl_impl) - writel_relaxed(config->asicctl, drvdata->base + ASICCTL); - writel_relaxed(config->ctiappset, drvdata->base + CTIAPPSET); + writel_relaxed(config->asicctl, reg_addr(drvdata, ASICCTL)); + writel_relaxed(config->ctiappset, reg_addr(drvdata, CTIAPPSET)); /* re-enable CTI */ writel_relaxed(1, drvdata->base + CTICONTROL); @@ -122,21 +132,22 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) return 0; } -u32 cti_read_single_reg(struct cti_drvdata *drvdata, int offset) +u32 cti_read_single_reg(struct cti_drvdata *drvdata, u32 off, u32 index) { - int val; + u32 val; CS_UNLOCK(drvdata->base); - val = readl_relaxed(drvdata->base + offset); + val = readl_relaxed(reg_index_addr(drvdata, off, index)); CS_LOCK(drvdata->base); return val; } -void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value) +void cti_write_single_reg(struct cti_drvdata *drvdata, u32 off, u32 index, + u32 value) { CS_UNLOCK(drvdata->base); - writel_relaxed(value, drvdata->base + offset); + writel_relaxed(value, reg_index_addr(drvdata, off, index)); CS_LOCK(drvdata->base); } @@ -149,7 +160,7 @@ void cti_write_intack(struct device *dev, u32 ackval) /* write if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIINTACK, ackval); + cti_write_single_reg(drvdata, CTIINTACK, 0, ackval); } /* @@ -322,7 +333,7 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, struct cti_config *config = &drvdata->config; u32 chan_bitmask; u32 reg_value; - int reg_offset; + u32 reg_offset; /* ensure indexes in range */ if ((channel_idx >= config->nr_ctm_channels) || @@ -344,8 +355,7 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, /* update the local register values */ chan_bitmask = BIT(channel_idx); - reg_offset = (direction == CTI_TRIG_IN ? CTIINEN(trigger_idx) : - CTIOUTEN(trigger_idx)); + reg_offset = (direction == CTI_TRIG_IN ? CTIINEN : CTIOUTEN); guard(raw_spinlock_irqsave)(&drvdata->spinlock); @@ -365,7 +375,8 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, reg_offset, reg_value); + cti_write_single_reg(drvdata, reg_offset, trigger_idx, + reg_value); return 0; } @@ -403,7 +414,7 @@ int cti_channel_gate_op(struct device *dev, enum cti_chan_gate_op op, if (err == 0) { config->ctigate = reg_value; if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIGATE, reg_value); + cti_write_single_reg(drvdata, CTIGATE, 0, reg_value); } return err; @@ -452,7 +463,7 @@ int cti_channel_setop(struct device *dev, enum cti_chan_set_op op, } if ((err == 0) && cti_is_active(config)) - cti_write_single_reg(drvdata, reg_offset, reg_value); + cti_write_single_reg(drvdata, reg_offset, 0, reg_value); return err; } diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 2bbfa405cb6b..7191a478b2da 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -171,7 +171,7 @@ static ssize_t coresight_cti_reg_show(struct device *dev, pm_runtime_get_sync(dev->parent); scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) - val = cti_read_single_reg(drvdata, cti_attr->off); + val = cti_read_single_reg(drvdata, cti_attr->off, cti_attr->index); pm_runtime_put_sync(dev->parent); return sysfs_emit(buf, "0x%x\n", val); @@ -192,7 +192,7 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, pm_runtime_get_sync(dev->parent); scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) - cti_write_single_reg(drvdata, cti_attr->off, val); + cti_write_single_reg(drvdata, cti_attr->off, cti_attr->index, val); pm_runtime_put_sync(dev->parent); return size; @@ -202,7 +202,8 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, (&((struct cs_off_attribute[]) { \ { \ __ATTR(name, 0444, coresight_cti_reg_show, NULL), \ - offset \ + offset, \ + 0 \ } \ })[0].attr.attr) @@ -211,7 +212,8 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, { \ __ATTR(name, 0644, coresight_cti_reg_show, \ coresight_cti_reg_store), \ - offset \ + offset, \ + 0 \ } \ })[0].attr.attr) @@ -219,7 +221,8 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, (&((struct cs_off_attribute[]) { \ { \ __ATTR(name, 0200, NULL, coresight_cti_reg_store), \ - offset \ + offset, \ + 0 \ } \ })[0].attr.attr) @@ -257,7 +260,7 @@ static ssize_t cti_reg32_show(struct device *dev, char *buf, scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { if (cti_is_active(config)) { - val = cti_read_single_reg(drvdata, reg_offset); + val = cti_read_single_reg(drvdata, reg_offset, 0); if (pcached_val) *pcached_val = val; } else if (pcached_val) { @@ -293,7 +296,7 @@ static ssize_t cti_reg32_store(struct device *dev, const char *buf, /* write through if offset and enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, reg_offset, val); + cti_write_single_reg(drvdata, reg_offset, 0, val); } return size; @@ -386,7 +389,7 @@ static ssize_t inen_store(struct device *dev, /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIINEN(index), val); + cti_write_single_reg(drvdata, CTIINEN, index, val); return size; } @@ -427,7 +430,7 @@ static ssize_t outen_store(struct device *dev, /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIOUTEN(index), val); + cti_write_single_reg(drvdata, CTIOUTEN, index, val); return size; } @@ -469,7 +472,7 @@ static ssize_t appclear_store(struct device *dev, /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIAPPCLEAR, val); + cti_write_single_reg(drvdata, CTIAPPCLEAR, 0, val); return size; } @@ -490,7 +493,7 @@ static ssize_t apppulse_store(struct device *dev, /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIAPPPULSE, val); + cti_write_single_reg(drvdata, CTIAPPPULSE, 0, val); return size; } diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index ef079fc18b72..98b8de8a3687 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -30,8 +30,8 @@ struct fwnode_handle; #define CTIAPPSET 0x014 #define CTIAPPCLEAR 0x018 #define CTIAPPPULSE 0x01C -#define CTIINEN(n) (0x020 + (4 * n)) -#define CTIOUTEN(n) (0x0A0 + (4 * n)) +#define CTIINEN 0x020 +#define CTIOUTEN 0x0A0 #define CTITRIGINSTATUS 0x130 #define CTITRIGOUTSTATUS 0x134 #define CTICHINSTATUS 0x138 @@ -217,8 +217,9 @@ int cti_enable(struct coresight_device *csdev, enum cs_mode mode, int cti_disable(struct coresight_device *csdev, struct coresight_path *path); void cti_write_all_hw_regs(struct cti_drvdata *drvdata); void cti_write_intack(struct device *dev, u32 ackval); -void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value); -u32 cti_read_single_reg(struct cti_drvdata *drvdata, int offset); +void cti_write_single_reg(struct cti_drvdata *drvdata, u32 off, u32 index, + u32 value); +u32 cti_read_single_reg(struct cti_drvdata *drvdata, u32 off, u32 index); int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, enum cti_trig_dir direction, u32 channel_idx, u32 trigger_idx); diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 770a8dc881b3..4aa25dda856c 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -68,6 +68,7 @@ struct cs_pair_attribute { struct cs_off_attribute { struct device_attribute attr; u32 off; + u32 index; }; ssize_t coresight_simple_show32(struct device *_dev, struct device_attribute *attr, char *buf); @@ -77,7 +78,8 @@ ssize_t coresight_simple_show_pair(struct device *_dev, struct device_attribute (&((struct cs_off_attribute[]) { \ { \ __ATTR(name, 0444, coresight_simple_show32, NULL), \ - offset \ + offset, \ + 0 \ } \ })[0].attr.attr) -- 2.43.0