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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bea917318esm10435555ad.5.2026.05.21.05.16.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 05:16:51 -0700 (PDT) From: Yingchao Deng Date: Thu, 21 May 2026 20:16:29 +0800 Subject: [PATCH v9 3/4] coresight: cti: add Qualcomm extended CTI identification and quirks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260521-extended_cti-v9-3-d21f4f92c51e@oss.qualcomm.com> References: <20260521-extended_cti-v9-0-d21f4f92c51e@oss.qualcomm.com> In-Reply-To: <20260521-extended_cti-v9-0-d21f4f92c51e@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jinlong.mao@oss.qualcomm.com, quic_yingdeng@quicinc.com, tingwei.zhang@oss.qualcomm.com, jie.gan@oss.qualcomm.com, Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779365796; l=7584; i=yingchao.deng@oss.qualcomm.com; s=20260521; h=from:subject:message-id; bh=9c3KkSTH9SNVjrN4djhgLnzm9UPZeM+m23N8Q7Og1Fk=; b=/W594KJ7Xc/7Ks61Cx8t6vxrj4Nq9aero4Jl+y3o9rkDDSgmPvVccZDPgqKD1KKcJXlJmz17p KeXqG+OCY/JAUw4y0F80ueg2V2inSchEFctQAGJp6mj1Ky0cVHcmiJs X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=YbHeeX0Qzqo7voZLva784lFhVChB9yF3a4sceW95ljA= X-Proofpoint-ORIG-GUID: UrOvmc1nrpeUXv2Pn8NyelUcAbjd3Lvg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIxMDEyMyBTYWx0ZWRfXzy7DqHthiYOT QF5oDhEcAtbgYURL7GY7MHkUydyf8w58JSzbrZhosroHbZfmEZV9qmIYit+kvLeMyBswX/N1qqc dF4ZBvP9vVRhB49hMJjVn4a4y/gZRmm63FOdYqmuARKegXEh5PUglad6P9FQZkb6VEtJW3tAbSS cEwhJJ9N1EfaFMGz8e48ccY8OvScKFWkBSrJyj4OcdOuq8MH3GKRfPV9pNvIpO4l1+ZBMO6q7J8 vMr9IMlNEHndiZDXZ+p7R0PxGOl6qOGtNRAgpqlnZpvydKbsaSww4CEWrMX/ggor23TzHK9iCTD 2vAh5p+2bxroKAzWcYqalzFkmrsHyTpHb8P8iE0sjYWuwRBJkQ6hFUdkTVJF7MARBvDI3XoGbfq 3fJjQt0gdnBgI8+OhPqFcCiEgj6JWUVCpkp1Hax83wUZD9cPGqFCpRAuP2ZPD3lRMXWE8s9UXPl kB3huFgvi8qOcXNh08A== X-Authority-Analysis: v=2.4 cv=YfyNIQRf c=1 sm=1 tr=0 ts=6a0ef7b5 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=yjDJaKUznl4u3GwUnvUA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: UrOvmc1nrpeUXv2Pn8NyelUcAbjd3Lvg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-21_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 suspectscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605210123 Qualcomm implements an extended variant of the ARM CoreSight CTI with a different register layout and vendor-specific behavior. While the programming model remains largely compatible, the register offsets differ from the standard ARM CTI and require explicit handling. Detect Qualcomm CTIs via the DEVARCH register and record this in the CTI driver data. Introduce a small mapping layer to translate standard CTI register offsets to Qualcomm-specific offsets, allowing the rest of the driver to use a common register access path. Additionally, handle a Qualcomm-specific quirk where the CLAIMSET register is incorrectly initialized to a non-zero value, which can cause tools or drivers to assume the component is already claimed. Clear the register during probe to reflect the actual unclaimed state. No functional change is intended for standard ARM CTI devices. Co-developed-by: Jinlong Mao Signed-off-by: Jinlong Mao Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-core.c | 27 +++++++++- drivers/hwtracing/coresight/coresight-cti.h | 7 ++- drivers/hwtracing/coresight/qcom-cti.h | 65 ++++++++++++++++++++++++ 3 files changed, 97 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c index c5cc2706e241..2dac5eb4ecca 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -21,6 +21,7 @@ #include "coresight-priv.h" #include "coresight-cti.h" +#include "qcom-cti.h" /* * CTI devices can be associated with a PE, or be connected to CoreSight @@ -45,6 +46,9 @@ static DEFINE_MUTEX(ect_mutex); static void __iomem *__reg_addr(struct cti_drvdata *drvdata, u32 off, u32 index) { + if (unlikely(rvdata->is_qcom_cti)) + off = cti_qcom_reg_off(off); + return drvdata->base + off + sizeof(u32) * index; } @@ -172,6 +176,9 @@ void cti_write_intack(struct device *dev, u32 ackval) /* DEVID[19:16] - number of CTM channels */ #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) +/* DEVARCH[31:21] - ARCHITECT */ +#define CTI_DEVARCH_ARCHITECT(devarch_val) ((int)BMVAL(devarch_val, 21, 31)) + static int cti_set_default_config(struct device *dev, struct cti_drvdata *drvdata) { @@ -702,6 +709,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) struct coresight_desc cti_desc; struct coresight_platform_data *pdata = NULL; struct resource *res = &adev->res; + u32 devarch; /* driver data*/ drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -726,6 +734,22 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) raw_spin_lock_init(&drvdata->spinlock); + devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH); + if (CTI_DEVARCH_ARCHITECT(devarch) == ARCHITECT_QCOM) { + drvdata->is_qcom_cti = true; + /* + * QCOM CTI does not implement Claimtag functionality as + * per CoreSight specification, but its CLAIMSET register + * is incorrectly initialized to 0xF. This can mislead + * tools or drivers into thinking the component is claimed. + * + * Reset CLAIMSET to 0 to reflect that no claims are active. + */ + CS_UNLOCK(drvdata->base); + writel_relaxed(0, drvdata->base + CORESIGHT_CLAIMSET); + CS_LOCK(drvdata->base); + } + /* initialise CTI driver config values */ ret = cti_set_default_config(dev, drvdata); if (ret) @@ -782,7 +806,8 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) /* all done - dec pm refcount */ pm_runtime_put(&adev->dev); - dev_info(&drvdata->csdev->dev, "CTI initialized\n"); + dev_info(&drvdata->csdev->dev, + "%sCTI initialized\n", drvdata->is_qcom_cti ? "QCOM " : ""); return 0; } diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index 98b8de8a3687..08ea6daf5b3c 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -54,10 +54,11 @@ struct fwnode_handle; /* * CTI CSSoc 600 has a max of 32 trigger signals per direction. * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def. + * QCOM CTI supports up to 128 trigger signals per direction. * Max of in and out defined in the DEVID register. * - pick up actual number used from .dts parameters if present. */ -#define CTIINOUTEN_MAX 32 +#define CTIINOUTEN_MAX 128 /** * Group of related trigger signals @@ -168,6 +169,9 @@ struct cti_config { * @spinlock: Control data access to one at a time. * @config: Configuration data for this CTI device. * @node: List entry of this device in the list of CTI devices. + * @is_qcom_cti: True if this CTI is a Qualcomm vendor-specific + * variant that requires register offset translation + * via cti_qcom_reg_off(). */ struct cti_drvdata { void __iomem *base; @@ -176,6 +180,7 @@ struct cti_drvdata { raw_spinlock_t spinlock; struct cti_config config; struct list_head node; + bool is_qcom_cti; }; /* diff --git a/drivers/hwtracing/coresight/qcom-cti.h b/drivers/hwtracing/coresight/qcom-cti.h new file mode 100644 index 000000000000..d3846613a0de --- /dev/null +++ b/drivers/hwtracing/coresight/qcom-cti.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _CORESIGHT_QCOM_CTI_H +#define _CORESIGHT_QCOM_CTI_H + +#include "coresight-cti.h" + +#define ARCHITECT_QCOM 0x477 + +/* CTI programming registers */ +#define QCOM_CTIINTACK 0x020 +#define QCOM_CTIAPPSET 0x004 +#define QCOM_CTIAPPCLEAR 0x008 +#define QCOM_CTIAPPPULSE 0x00C +#define QCOM_CTIINEN 0x400 +#define QCOM_CTIOUTEN 0x800 +#define QCOM_CTITRIGINSTATUS 0x040 +#define QCOM_CTITRIGOUTSTATUS 0x060 +#define QCOM_CTICHINSTATUS 0x080 +#define QCOM_CTICHOUTSTATUS 0x084 +#define QCOM_CTIGATE 0x088 +#define QCOM_ASICCTL 0x08C +/* Integration test registers */ +#define QCOM_ITCHINACK 0xE70 +#define QCOM_ITTRIGINACK 0xE80 +#define QCOM_ITCHOUT 0xE74 +#define QCOM_ITTRIGOUT 0xEA0 +#define QCOM_ITCHOUTACK 0xE78 +#define QCOM_ITTRIGOUTACK 0xEC0 +#define QCOM_ITCHIN 0xE7C +#define QCOM_ITTRIGIN 0xEE0 + +static inline u32 cti_qcom_reg_off(u32 offset) +{ + switch (offset) { + case CTIINTACK: return QCOM_CTIINTACK; + case CTIAPPSET: return QCOM_CTIAPPSET; + case CTIAPPCLEAR: return QCOM_CTIAPPCLEAR; + case CTIAPPPULSE: return QCOM_CTIAPPPULSE; + case CTIINEN: return QCOM_CTIINEN; + case CTIOUTEN: return QCOM_CTIOUTEN; + case CTITRIGINSTATUS: return QCOM_CTITRIGINSTATUS; + case CTITRIGOUTSTATUS: return QCOM_CTITRIGOUTSTATUS; + case CTICHINSTATUS: return QCOM_CTICHINSTATUS; + case CTICHOUTSTATUS: return QCOM_CTICHOUTSTATUS; + case CTIGATE: return QCOM_CTIGATE; + case ASICCTL: return QCOM_ASICCTL; + case ITCHINACK: return QCOM_ITCHINACK; + case ITTRIGINACK: return QCOM_ITTRIGINACK; + case ITCHOUT: return QCOM_ITCHOUT; + case ITTRIGOUT: return QCOM_ITTRIGOUT; + case ITCHOUTACK: return QCOM_ITCHOUTACK; + case ITTRIGOUTACK: return QCOM_ITTRIGOUTACK; + case ITCHIN: return QCOM_ITCHIN; + case ITTRIGIN: return QCOM_ITTRIGIN; + + default: + return offset; + } +} + +#endif /* _CORESIGHT_QCOM_CTI_H */ -- 2.43.0