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From: Conor Dooley <conor@kernel.org>
To: Conor Dooley <conor@kernel.org>,
	Jonathan Cameron <jic23@kernel.org>,
	Paul Walmsley <pjw@kernel.org>,
	Samuel Holland <samuel.holland@sifive.com>,
	Dominique Belhachemi <domibel@debian.org>
Cc: Conor Dooley <conor.dooley@microchip.com>,
	Emil Renner Berthing <kernel@esmil.dk>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] cache: sifive_ccache: Add StarFive JH7110 SoC support
Date: Thu, 21 May 2026 11:12:52 +0100	[thread overview]
Message-ID: <20260521-treble-bootlace-29788b4cd86f@spud> (raw)
In-Reply-To: <20260430035259.3402954-1-domibel@debian.org>

From: Conor Dooley <conor.dooley@microchip.com>

On Thu, 30 Apr 2026 03:52:59 +0000, Dominique Belhachemi wrote:
> This cache controller is also used on the StarFive JH7110 SoC. It does
> not have the data-uncorrectable ECC quirk that JH7100 has, so only
> QUIRK_NONSTANDARD_CACHE_OPS is set.

Applied to riscv-soc-for-next, thanks!

[1/1] cache: sifive_ccache: Add StarFive JH7110 SoC support
      https://git.kernel.org/conor/c/8e2501e1494c

Thanks,
Conor.

      parent reply	other threads:[~2026-05-21 10:14 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-30  3:52 Dominique Belhachemi
2026-04-30 19:13 ` Conor Dooley
2026-04-30 23:39   ` Dominique Belhachemi
2026-05-21 10:12 ` Conor Dooley [this message]

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