From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C26D1264617 for ; Thu, 21 May 2026 01:42:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779327760; cv=none; b=bBIuISoZV4VA+DSidPSICANpgcr226osMuC6aYN9W5r+hcQHKfMMATmDASH/KycgTf1/tGhj/5Vb8JYLW8DVf992TBKDcSOgEVy5mbn598XHzuAPS7Q+qv/MSh03U++/4/h8j4EMbDtTqJ9J9QDNJayATP6jGilssmz+WRmZr2E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779327760; c=relaxed/simple; bh=y0eLfdlKOsnXKLcqHgoMoE6tZoZpJ5wRnAmYHP8/7DA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IfJK8HCoFR9ScDqLI2BzPqSSD4eaqAzCoRUqB3X05rSizLYk74+LQnlK6rZ4cPVifc7iBkzCynipYx+4gnJ3eYBxoVmEdnPxyAFYF/IITGdGNPV1poFUDPRNb7wevcFJnWO7/mDDexcmRNNQIlgs6U7QQ2I6IFJU1t817kIvYkI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=L1BK6VZx; arc=none smtp.client-ip=209.85.210.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="L1BK6VZx" Received: by mail-pf1-f172.google.com with SMTP id d2e1a72fcca58-82f8893bff3so2551274b3a.2 for ; Wed, 20 May 2026 18:42:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779327751; x=1779932551; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XQHAOKYoNq3MrKqMcGhimP9jof0s1tqXQowtY/BWP0g=; b=L1BK6VZx19VgAMtp65r9FWnqF7rP1jOl0JYYjN+Tt4HRrum/ClJ3HCvDrXduYkNlnJ Dq0SPZazzpE4I33zmPGut+mglgPsfw0OfZkGADudCLd99wQPSOIQorITloL5L/tJkpkA m95kUIL8NhDdnuqjBg03MIQFdyC9W0osynyAI27cqYPr/Jajn0Mj2UB1vozz3GeDVC9e ULHpN/V48l4EIvXztKWeMOZx93edWx7kmqi9v4lr9CcIte/thtPK0fG5OgEMzo2kx+cL P7yph36LPIXwh8YibohcjJSe1dKzzj/K4oDW6ij+GJwKQ6KqMofry5fKyV2dWKALpag7 mRjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779327751; x=1779932551; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=XQHAOKYoNq3MrKqMcGhimP9jof0s1tqXQowtY/BWP0g=; b=KtaqJdJv42vQKeb4HaGKk+mFjZqOAEt4+abvgQyvBp2QB/V1OheKCVqDbm9ZwCSKjj XJ5DQqB0ioUC89vWHdV+QK5s9glbH1SoY+/kFxaYYUB0OC6E6QnnL4ovdv+GcaGVLtzo z0lYJDo/X4oAb5p67Dp7eI7HBGoHC7p0v5t10MWpIkv5foPjua+uPrYpmzW/Br2d3+sS QwbUsupi/51cLtHUBPOsK/mePNbJvqfp0sYlFcG07dATz/WaePpjljMfO6ol/NFvsBKb LHmkVwMG9/pwB0rqPcXiuD9DM6HG79WeDghQLhCOnSimdmaH99AOR5347nsfQ88pPdyV YB0w== X-Forwarded-Encrypted: i=1; AFNElJ/CoXsSx35e01CpkMrLXOXgUf/l/1mVrT6LQl4dAGit7A4VOvbcR8N0rSCUJYRZRBGB6kdMc0oIkDLLgIE=@vger.kernel.org X-Gm-Message-State: AOJu0YxxKn3djpHQvGfACM7rLk4qUvS0ofO1kdFzxEyrI314s9M/MEib /+qM9RRyVH/GW7dsSuMvF06FxFO9xwN12elFelAHJgOm4DncQMbL6Gi5 X-Gm-Gg: Acq92OGghex/QAW1eMy10rvLYF8w6Dr9jR0BnVH6H13i9rQm4MqOv92ifSbABSrmn9l mFRrxeiS9hiRFI+M34iWxv7EMTDofdOLYSWZlD6k0opEPpKAIat9tnVcsqx5D+tN1Z5WL+L2IQs 6grixv0+tyVJje9qG49RPXR2n6i4yTGt3m29tJN93esyaapl93U+jYNw2HhfxS6fboazSbiE5tW rtkNj5FELqsta6JJDbfLjrYjTZtllcWnNy8s66tRB/fAJx1RNfe8odJJUWx+rB5VM3m+3ayaDP/ wq9KmG/sXM+uOl70reQIWs79Oaej3kEbPvJ9aAfyOadlZzPty+ozsz1sk8vIT7zuC01f2g8vjbV OZ34ttdQtsy7LA1fKGiBRWdrB+pXM/mBhURC7umKdumKAlHv8gpBQYePdB7mHsvA0ZjHDdLxFdb 0zKaYAkJG65c5ctz0FZOcMWnBnqzct4IiPD/jfHNBgdGSaJtGUXjEvVGqnx/zHe1osa/wPEslsI kl45iP9qASG X-Received: by 2002:a05:6a00:2e9e:b0:82f:61f5:1d7 with SMTP id d2e1a72fcca58-8414ade9c4dmr784283b3a.25.1779327750726; Wed, 20 May 2026 18:42:30 -0700 (PDT) Received: from localhost.localdomain (60-250-196-139.hinet-ip.hinet.net. [60.250.196.139]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f19fa869esm26411475b3a.61.2026.05.20.18.42.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2026 18:42:30 -0700 (PDT) From: Joey Lu To: mturquette@baylibre.com, sboyd@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v3 2/3] clk: nuvoton: ma35d1: fix PLL_CTL1_FRAC bit field width and fractional calc Date: Thu, 21 May 2026 09:42:19 +0800 Message-ID: <20260521014220.77955-3-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260521014220.77955-1-a0987203069@gmail.com> References: <20260521014220.77955-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit PLL_CTL1_FRAC was defined as GENMASK(31, 24), covering only 8 bits. The hardware fractional field occupies bits [31:8] (24 bits), so the mask must be GENMASK(31, 8). The previous fractional-mode calculation used FIELD_MAX(PLL_CTL1_FRAC) as the denominator to obtain 2 decimal places. With the corrected 24-bit mask the old divisor is wrong; replace the arithmetic with a proper 24-bit fixed-point rounding to 3 decimal places using the kernel's DIV_ROUND_CLOSEST_ULL helper: n_frac = n * 1000 + DIV_ROUND_CLOSEST_ULL(x * 1000, 1 << 24) Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock controller") Signed-off-by: Joey Lu --- drivers/clk/nuvoton/clk-ma35d1-pll.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/nuvoton/clk-ma35d1-pll.c b/drivers/clk/nuvoton/clk-ma35d1-pll.c index bfedd45bd04b..eb9d69d2077b 100644 --- a/drivers/clk/nuvoton/clk-ma35d1-pll.c +++ b/drivers/clk/nuvoton/clk-ma35d1-pll.c @@ -48,7 +48,7 @@ #define PLL_CTL1_PD BIT(0) #define PLL_CTL1_BP BIT(1) #define PLL_CTL1_OUTDIV GENMASK(6, 4) -#define PLL_CTL1_FRAC GENMASK(31, 24) +#define PLL_CTL1_FRAC GENMASK(31, 8) #define PLL_CTL2_SLOPE GENMASK(23, 0) #define INDIV_MIN 1 @@ -113,9 +113,9 @@ static unsigned long ma35d1_calc_pll_freq(u8 mode, u32 *reg_ctl, unsigned long p pll_freq = div_u64(pll_freq, m * p); } else { x = FIELD_GET(PLL_CTL1_FRAC, reg_ctl[1]); - /* 2 decimal places floating to integer (ex. 1.23 to 123) */ - n = n * 100 + ((x * 100) / FIELD_MAX(PLL_CTL1_FRAC)); - pll_freq = div_u64(parent_rate * n, 100 * m * p); + /* convert 24-bit fraction to 3 decimal digits, rounding to closest */ + n = n * 1000 + DIV_ROUND_CLOSEST_ULL((u64)x * 1000, 1ULL << 24); + pll_freq = div_u64((u64)parent_rate * n, 1000 * m * p); } return pll_freq; } -- 2.43.0