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Fri, 22 May 2026 04:10:28 -0700 (PDT) Received: from hu-nmalempa-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-841648a2bf2sm1578962b3a.0.2026.05.22.04.10.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2026 04:10:27 -0700 (PDT) From: Navya Malempati Subject: [PATCH 0/2] Remove gold/silver_cpu_sleep idle states for lemans and monaco Date: Fri, 22 May 2026 16:40:12 +0530 Message-Id: <20260522-ml_cpuidle-v1-0-fd311cf33fb4@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAJQ5EGoC/yXM3wpAMBSA8VfRubaaCfEqkmY7OPKvDam1dzdc/ i6+z4FFQ2ihihwYvMjStgYkcQRqlOuAjHQwCC5yngnBlrlV+0l6RqYlT4uizHKtOIRgN9jT/c3 q5rc9uwnV8R7A+wcmOssnbgAAAA== X-Change-ID: 20260522-ml_cpuidle-da0377956dc0 To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Navya Malempati X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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However, CPU power collapse mode is often not utilized in favor of performance. Remove CPU power collapse modes for lemans and monaco as well aligning with SM8350/SM8450/SM8550/SM8650. --- Navya Malempati (2): arm64: dts: qcom: monaco: Remove the little/big_cpu_sleep_0 idle states arm64: dts: qcom: lemans: Remove the gold_cpu_sleep idle state arch/arm64/boot/dts/qcom/lemans.dtsi | 36 +++++++++--------------------------- arch/arm64/boot/dts/qcom/monaco.dtsi | 36 ++++++++---------------------------- 2 files changed, 17 insertions(+), 55 deletions(-) --- base-commit: 550604d6c9b9efc8d068aff94dc301694a7afdee change-id: 20260522-ml_cpuidle-da0377956dc0 Best regards, -- Navya Malempati