From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EA363D45C5; Fri, 22 May 2026 10:18:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779445113; cv=none; b=mhR3eQZkeYbbz3K9FTJXSXzfA9i/3uV247D4b3Lnht0Han6BZ9hZoBov0Rhb2nWgFDBnonVywg+LjbrwU8Fwb1rQXE5pWuEK0HINk8/7VRJrsFoP6/ymEKNbGxGkKFalGUo5UhuZodH5FGEVTQu3VSi7t6UEw5o0C7kbOe5dVgc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779445113; c=relaxed/simple; bh=CSU7J8SwuiLtOiP4Am1H8eZ4uiZ6BrvsQHIE+i4cp0Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GyURJjCW9xyoloof93Pchs99v5/X6BIQkJFB6+PVJBE5coJvMqJ3SM5sG6XaV1ccMZttclMX2e8SH/zAc2sBeYY3ZkhNQPk9VrNySk50UDQ54W6SSy+AherkVzIyZqZkA2K3qgTQ0rGAdWjYcTYtR5zXKoALLMQVkibVaXn/ktY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZSnOUwuW; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZSnOUwuW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 202461F00A3D; Fri, 22 May 2026 10:18:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779445111; bh=3tvkeAA8mee6Hl0XfVK6GmwDt+kgUaPqK4c7VFuVgTk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=ZSnOUwuW67UQ68iFvnK3WZeivbB9JWRzW5+LVMFaKrHy3bgjO+ZcND5iSGaoGZVFq J6RegIHBxLapEKkpfLHXGZpQ5Yax2RxRoOaz464jx/1EeAU2AaeLjjE+jftMrYW+4z WvcCBar2+bBbi3wKcm6XWzOjUVTg6j7on/V0A0KANhaKY2VdVeCwEp1BbmwZWOt1ek ZJEpPjyuv2utJ+bunSttFuXTproF/Ubhnx1sTt4Np6dZrEoG2POEcIaSOHlFtdix4A 6cYMTSnp0YqsXSxBPVrVXuOEnI/zg3ZPOI4UdHrsvoBM7hZyB8/eCPkTiRgLfV5KjQ vqU27GIP+Vq0Q== From: Claudiu Beznea To: wsa+renesas@sang-engineering.com, tommaso.merciai.xr@bp.renesas.com, alexandre.belloni@bootlin.com, Frank.Li@nxp.com, p.zabel@pengutronix.de Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea , stable@vger.kernel.org Subject: [PATCH 03/17] i3c: renesas: Restore STDBR and EXTBR registers on resume Date: Fri, 22 May 2026 13:18:01 +0300 Message-ID: <20260522101815.1722909-4-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522101815.1722909-1-claudiu.beznea@kernel.org> References: <20260522101815.1722909-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Claudiu Beznea The Renesas RZ/G3S supports a power saving state where power to the most SoC componentes (including I3C) is lost. The STDBR and EXTBR are configured in initialization phase though the struct i3c_master_controller_ops::bus_init. Set them on resume function as well to keep the same state of the controller after a suspend with power loss and a similar initialization sequence as in bus_init. Fixes: e7218986319b ("i3c: renesas: Add suspend/resume support") Cc: stable@vger.kernel.org Signed-off-by: Claudiu Beznea --- drivers/i3c/master/renesas-i3c.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/i3c/master/renesas-i3c.c b/drivers/i3c/master/renesas-i3c.c index 1917549cf6d5..6c23f956ad2a 100644 --- a/drivers/i3c/master/renesas-i3c.c +++ b/drivers/i3c/master/renesas-i3c.c @@ -260,6 +260,7 @@ struct renesas_i3c { u32 dyn_addr; u32 i2c_STDBR; u32 i3c_STDBR; + u32 extbr; unsigned long rate; u8 addrs[RENESAS_I3C_MAX_DEVS]; struct renesas_i3c_xferqueue xferqueue; @@ -607,10 +608,9 @@ static int renesas_i3c_bus_init(struct i3c_master_controller *m) renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR); /* Extended Bit Rate setting */ - renesas_writel(i3c->regs, EXTBR, EXTBR_EBRLO(od_low_ticks) | - EXTBR_EBRHO(od_high_ticks) | - EXTBR_EBRLP(pp_low_ticks) | - EXTBR_EBRHP(pp_high_ticks)); + i3c->extbr = EXTBR_EBRLO(od_low_ticks) | EXTBR_EBRHO(od_high_ticks) | + EXTBR_EBRLP(pp_low_ticks) | EXTBR_EBRHP(pp_high_ticks); + renesas_writel(i3c->regs, EXTBR, i3c->extbr); renesas_writel(i3c->regs, REFCKCTL, REFCKCTL_IREFCKS(cks)); i3c->refclk_div = cks; @@ -1447,6 +1447,8 @@ static int renesas_i3c_resume_noirq(struct device *dev) goto err_tresetn; /* Re-store I3C registers value. */ + renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR); + renesas_writel(i3c->regs, EXTBR, i3c->extbr); renesas_writel(i3c->regs, REFCKCTL, REFCKCTL_IREFCKS(i3c->refclk_div)); renesas_writel(i3c->regs, MSDVAD, MSDVAD_MDYADV | -- 2.43.0