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Sun, 24 May 2026 08:38:48 -0700 From: Edward Srouji Date: Sun, 24 May 2026 18:38:05 +0300 Subject: [PATCH rdma-next 4/8] RDMA/mlx5: Support deferred rate limit configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260524-packet-pacing-v1-4-3d79439f8d08@nvidia.com> References: <20260524-packet-pacing-v1-0-3d79439f8d08@nvidia.com> In-Reply-To: <20260524-packet-pacing-v1-0-3d79439f8d08@nvidia.com> To: Leon Romanovsky , Saeed Mahameed , Tariq Toukan , Mark Bloch , "Jason Gunthorpe" , Selvin Xavier , "Kalesh AP" , Abhijit Gangurde , Allen Hubbe CC: , , , Edward Srouji , "Maher Sanalla" , Michael Guralnik X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779637112; l=2893; i=edwards@nvidia.com; s=20251029; h=from:subject:message-id; bh=08RdpkAd8x4ORVw/pTBMEhLI+WWenUoFVQjGVkVNC+I=; b=SDOTkpe0qCBwNu9tvGYtza71LiY3sRtpQciDAY8CrUyBgZLX4X9z2kSNNZa6vMbD3JCPB+zy+ ioGkQvilrG1Cwg6zwmbD1YgeZtz0mK+dMo7H5H37NEeS31c4oBGvp4B X-Developer-Key: i=edwards@nvidia.com; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0BBQzb7KFZEPdRoZMZiN7SbdbJuWIOkToRFjyPsvoLN2GixkpD1vcLRnDaKKQlx0jYOw+TzyP40D3fqJ6RAO6Pf1h1tq+iq3DNn38997Vc09atoICKxS29XaO/ZgZ462wdPjXgzk87B+eh/bAnpaO6GBCJVgxZuu8aohT9s4w9zKUolZb5mcUXPupRiyMqOdlVMDMhrcpHlLMuz8Npkz6ROMtwpPTSFf8LxWwYFsukNzUXPKgQhfs0RYRpxfe+DEfQuv6ibYEFa8wP8AgQArxLBaKeH3+TTci8whTIDQxehBjk0jMAegYHy7+qFJq8m9ip5/mmQmxlu2ds9huwer0PHNgOT/GcizOiHKrtocQxr6aq3g0wWAMb++rKVqvY+gx0x+6TzTQQU6FKKT5rKqNZmIA7B+1KjeGLpj6DgeJhvIdiFVnylm6gxaSgHbjBnq X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2026 15:39:02.7417 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c89feacb-0104-43bf-244a-08deb9aa9502 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9278 From: Maher Sanalla Allow passing a rate limit attribute in modify QP flows even when the QP is in a state that does not support packet pacing programming in the lower layers. When the user sets a rate limit during a QP transition that is not to RTS, store the value in the mlx5 QP struct and program it to FW when the QP later transitions to RTS, which is the state that allows configuring the rate limit index in the QP context. Signed-off-by: Maher Sanalla Reviewed-by: Michael Guralnik Signed-off-by: Edward Srouji --- drivers/infiniband/hw/mlx5/mlx5_ib.h | 1 + drivers/infiniband/hw/mlx5/qp.c | 14 +++++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/mlx5/mlx5_ib.h b/drivers/infiniband/hw/mlx5/mlx5_ib.h index e156dc4d752996cc4ae465bb567b0c1305d07fed..c74a53da99393cf4d4c0823cd12f9eccaa28f212 100644 --- a/drivers/infiniband/hw/mlx5/mlx5_ib.h +++ b/drivers/infiniband/hw/mlx5/mlx5_ib.h @@ -536,6 +536,7 @@ struct mlx5_ib_qp { struct list_head cq_recv_list; struct list_head cq_send_list; struct mlx5_rate_limit rl; + struct mlx5_rate_limit rl_desired; u32 underlay_qpn; u32 flags_en; /* diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c index e96d26253e3b1fabee23947b1a61ab26e7c7067f..66ab16b017c8311d44b521c023cfaf23ac42190a 100644 --- a/drivers/infiniband/hw/mlx5/qp.c +++ b/drivers/infiniband/hw/mlx5/qp.c @@ -3946,7 +3946,11 @@ static void qp_rl_commit(struct mlx5_core_dev *dev, if (qp->rl.rate) mlx5_rl_remove_rate(dev, &qp->rl); memset(&qp->rl, 0, sizeof(qp->rl)); + memset(&qp->rl_desired, 0, sizeof(qp->rl_desired)); + return; } + + qp->rl_desired = ctx->rl_desired; } static int modify_raw_packet_qp_sq( @@ -3990,6 +3994,7 @@ static int modify_raw_packet_qp_sq( if (new_state != MLX5_SQC_STATE_RDY) { mlx5_rl_remove_rate(dev, &ibqp->rl); memset(&ibqp->rl, 0, sizeof(ibqp->rl)); + memset(&ibqp->rl_desired, 0, sizeof(ibqp->rl_desired)); } sq->state = new_state; @@ -4449,7 +4454,7 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, if (err) goto out; } else { - rl_ctx.rl_desired = qp->rl; + rl_ctx.rl_desired = qp->rl_desired; } op = optab[mlx5_cur][mlx5_new]; @@ -4833,6 +4838,13 @@ int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, attr_mask); goto out; } + } else if (attr_mask == IB_QP_RATE_LIMIT && cur_state != IB_QPS_RTS) { + struct mlx5_rate_limit rl_desired = {}; + + err = qp_rl_parse(dev, qp, attr, &ucmd, &rl_desired); + if (!err) + qp->rl_desired = rl_desired; + goto out; } else if (qp_type != MLX5_IB_QPT_REG_UMR && qp_type != MLX5_IB_QPT_DCI && !ib_modify_qp_is_ok(cur_state, new_state, qp_type, -- 2.49.0