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Sun, 24 May 2026 06:13:46 -0700 (PDT) Received: from guoguo-lecoo.lan ([104.28.159.63]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84164fb28d5sm7163128b3a.41.2026.05.24.06.13.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 May 2026 06:13:46 -0700 (PDT) From: Chuanhong Guo Subject: [PATCH v2 0/3] clk: add Siflower SF21 topcrm support Date: Sun, 24 May 2026 21:13:05 +0800 Message-Id: <20260524-sf21-topcrm-v2-0-4527aae05c3d@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAAAAAAAC/1XMTQrCMBCG4auUWTuSHxODK+8hXdSYtAOmKUkJS sndjQUXLt8ZvmeD7BK5DJdug+QKZYpzC3HowE7DPDqkR2sQTGimuMLsBcc1LjYF5EZpy9Rdc2m gLZbkPL127da3niivMb13vPDv9eec/5zCkeFJGi9c+0nvr2MY6Hm0MUBfa/0A4l5N6KYAAAA= X-Change-ID: 20260515-sf21-topcrm-1856c05b6138 To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Yao Zi Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Chuanhong Guo X-Mailer: b4 0.14.3 Siflower SF21A6826 and SF21H8898 are RISC-V chips with quad-core T-Head C908 for home routers and gateways. This series adds the initial RISC-V Kconfig entry for Siflower SoCs and support for the toplevel clock and reset module on Siflower SF21 socs. Signed-off-by: Chuanhong Guo --- Changes in v2: - drop "if TTY" condition in ARCH_SIFLOWER - drop "xin25m" in dt bindings for the possibility of a different xtal frequency. - use index instead of fw_name for xtal clock in the driver. - drop unnecessary fixed-clock node in dt binding example. - name the top node "soc" instead of "/" to fix binding check failure on missing "model" and "compatible". - drop SF21_RESET_MAX, rename SF21_CLK_MAX to SF21_NUM_CLKS and define it in driver instead of binding header. - split dt binding header into separated clock and reset headers. - sort headers in the driver - add a shared sf21_dual_dividers for the two dividers in series in CMNPLL and PCIEPLL. - multiply before divide for PLL VCO calculations. - change cpu and pic clock flags from ignore_unused to is_critical. - use guard macro for spinlocks. - split clock and reset locks and use raw_spinlock for clock lock. - select RATIONAL in Kconfig for clk driver. - use FIELD_MAX instead of BIT(x) - 1 for field max value. - Link to v1: https://lore.kernel.org/r/20260517-sf21-topcrm-v1-0-438f2e0513ff@gmail.com --- Chuanhong Guo (3): riscv: add Siflower RISC-V SoC family Kconfig support dt-bindings: clock: add header/doc for Siflower sf21-topcrm clk: add support for siflower sf21-topcrm .../bindings/clock/siflower,sf21-topcrm.yaml | 60 ++ arch/riscv/Kconfig.socs | 7 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/siflower/Kconfig | 23 + drivers/clk/siflower/Makefile | 1 + drivers/clk/siflower/clk-sf21-topcrm.c | 1017 ++++++++++++++++++++ include/dt-bindings/clock/siflower,sf21-topcrm.h | 42 + include/dt-bindings/reset/siflower,sf21-topcrm.h | 25 + 9 files changed, 1177 insertions(+) --- base-commit: c1ecb239fa3456529a32255359fc78b69eb9d847 change-id: 20260515-sf21-topcrm-1856c05b6138 Best regards, -- Chuanhong Guo