From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EA9A33A6E2 for ; Mon, 25 May 2026 18:21:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779733307; cv=none; b=SjdXp3E4S8CatpRNg+yt62o/5ZOEXQQl1iGFms/+oNBvhsPbBbvsOhIAhTCq2E8Prml4jJqjzc6Nt+wxZKw72fT+Ddk5AS42aeYQTAxkKBm58Wr4RniUnBwr19jtpGG7MNn3s71MbiWWnRea1mR58q6de+ww9eDQMxKLawBJXYk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779733307; c=relaxed/simple; bh=Ruugzh42ITQh/fqODZIPfjlQkacKRsNly6oM2w/miVY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cvEaITTwlG886YiL+wUqKJSAyaJp+dOXmuRRr9TqV2OiII/+BcxcYHcu6wlRud/z74u9V0LJQasAxvwcb0Uc/9wLPP9wwyttLGx9jVrFqtFpxuULs78wH95hQz/tCjBxq8YUcT5UIFMBiZPHhh/zT8DxCpQM8A8LfaAF3GU0Jjw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=eW5BC7eK; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="eW5BC7eK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779733305; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gC5zr5yw5wsDg+aceJ8pufnQOHytYxuE6r2DcXf4+O0=; b=eW5BC7eKABR4VkWO9ijP6HS/JWdZ9OvVzZ/HvWrJUBpLC3ndFFxIuBqXrtElBu0vmeT0Hl oQgQwDnIfKsfUnKqljeEOR6D1e3FKEPkpw+PaGolaBVba8wVFZxQ2sw0ATJjQuf5aY19Iu ItK/MDjE1ccmwI5CpjHx4gvk3OqxWWI= Received: from mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-167-Qc8-3Xy5N0C2ACylguXNuA-1; Mon, 25 May 2026 14:21:42 -0400 X-MC-Unique: Qc8-3Xy5N0C2ACylguXNuA-1 X-Mimecast-MFC-AGG-ID: Qc8-3Xy5N0C2ACylguXNuA_1779733300 Received: from mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 666721956089; Mon, 25 May 2026 18:21:39 +0000 (UTC) Received: from jtaubepe-thinkpadx1carbongen12.ibmlowe.csb (unknown [10.22.64.142]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id AF3841800347; Mon, 25 May 2026 18:21:34 +0000 (UTC) From: Jesse Taube To: linux-riscv@lists.infradead.org Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Conor Dooley , Icenowy Zheng , Jesse Taube , Jisheng Zhang , linux-kernel@vger.kernel.org, Jesse Taube Subject: [PATCH v7 2/2] clocksource/drivers/timer-clint: Add T-Head C9xx clint Date: Mon, 25 May 2026 14:21:24 -0400 Message-ID: <20260525182124.19402-2-jtaubepe@redhat.com> In-Reply-To: <20260525182124.19402-1-jtaubepe@redhat.com> References: <20260525182124.19402-1-jtaubepe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 From: Jisheng Zhang To use the T-HEAD C9xx clint in RISCV-M NOMMU env, we need to take care two points: 1.The mtimecmp in T-Head C9xx clint only supports 32bit read/write, implement such support. 2. As pointed out by commit ca7810aecdba ("lib: utils/timer: mtimer: add a quirk for lacking mtime register") of opensbi: "T-Head developers surely have a different understanding of time CSR and CLINT's mtime register with SiFive ones, that they did not implement the mtime register at all -- as shown in openC906 source code, their time CSR value is just exposed at the top of their processor IP block and expects an external continuous counter, which makes it not overrideable, and thus mtime register is not implemented, even not for reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS extended CSR, these systems still rely on the mtimecmp registers to generate timer interrupts. This makes it necessary to implement T-Head C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing reading mtime register and falls back to default code that reads time CSR." So, we need to fall back to read time CSR instead of mtime register using RISCV_ISA_EXT_ZICNTR. Signed-off-by: Jisheng Zhang Signed-off-by: Jesse Taube --- Treat this as a completely new patch, as it is mostly rewritten. Original: https://lore.kernel.org/all/20240410142347.964-3-jszhang@kernel.org/ V6 -> V7: - New commit - Split csr and c900 parts into different commits - c900_clint_clock_next_event use csr_get_cycles64 over accedental use of clint_get_cycles64 --- drivers/clocksource/timer-clint.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c index 18f7bf7d26c6..62fe28df73fb 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -39,6 +39,7 @@ static u64 __iomem *clint_timer_cmp; static u64 __iomem *clint_timer_val; static unsigned long clint_timer_freq; static unsigned int clint_timer_irq; +static bool is_c900_clint; #ifdef CONFIG_RISCV_M_MODE u64 __iomem *clint_time_val; @@ -154,6 +155,19 @@ static int clint_clock_next_event(unsigned long delta, return 0; } +static int c900_clint_clock_next_event(unsigned long delta, + struct clock_event_device *ce) +{ + void __iomem *r = clint_timer_cmp + + cpuid_to_hartid_map(smp_processor_id()); + u64 val = csr_get_cycles64() + delta; + + csr_set(CSR_IE, IE_TIE); + writel_relaxed(val, r); + writel_relaxed(val >> 32, r + 4); + return 0; +} + static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) = { .name = "clint_clockevent", .features = CLOCK_EVT_FEAT_ONESHOT, @@ -168,6 +182,9 @@ static int clint_timer_starting_cpu(unsigned int cpu) if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZICNTR)) ce->set_next_event = clint_clock_next_event; + if (is_c900_clint) + ce->set_next_event = c900_clint_clock_next_event; + ce->cpumask = cpumask_of(cpu); clockevents_config_and_register(ce, clint_timer_freq, 100, ULONG_MAX); @@ -319,8 +336,16 @@ static int __init clint_timer_init(struct device_node *np) static int __init clint_timer_init_dt(struct device_node *np) { + is_c900_clint = false; + return clint_timer_init(np); +} + +static int __init c900_clint_timer_init_dt(struct device_node *np) +{ + is_c900_clint = true; return clint_timer_init(np); } TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt); TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt); +TIMER_OF_DECLARE(clint_timer2, "thead,c900-clint", c900_clint_timer_init_dt); -- 2.54.0