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Tue, 26 May 2026 07:42:11 -0700 (PDT) Received: from hu-bibekkum-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84164acc288sm15362019b3a.10.2026.05.26.07.42.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 May 2026 07:42:11 -0700 (PDT) From: Bibek Kumar Patro Subject: [PATCH v2 0/6] iommu/arm-smmu: Add interconnect bandwidth voting support Date: Tue, 26 May 2026 20:12:01 +0530 Message-Id: <20260526-smmu_interconnect_addition-v2-0-2a6d8ca30d63@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIADqxFWoC/x3MQQqAIBBA0avErBPK0KirRIQ4U82iKdQiiO6et HyL/x+IFJgi9MUDgS6OvEuGLgvwq5OFFGM26ErbytRWxW07J5ZEwe8i5NPkEDnlTGFnbGsaQx2 2kAdHoJnvfz6M7/sBQV7ISmwAAAA= X-Change-ID: 20260516-smmu_interconnect_addition-d9567535e9d7 To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Bibek Kumar Patro X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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In the common case this vote is held implicitly by other clients (e.g. the GMU device holds a GEM_NOC vote whenever the GPU is active), so the SMMU works without any explicit vote from the driver. However, during certain power transitions — specifically sleep/wakeup sequences — the interconnect vote can be dropped before the SMMU is powered down. If the SMMU is then accessed (e.g. during runtime resume) while the vote is absent, register reads fail intermittently. The precise ordering makes this difficult to reproduce consistently. This series adds support for an optional interconnect path in the arm-smmu driver. When an 'interconnects' property is present in the SMMU device node, the driver acquires the path and votes for bandwidth before any register access, releasing the vote on runtime suspend and on error paths. Platforms that do not describe an interconnect path are unaffected. Changes in v2: - dt-bindings: Cleaned up 'interconnects' property description — removed "Optional" prefix and driver implementation details as flagged by Krzysztof Kozlowski. - dt-bindings: Added allOf conditional using 'items' to restrict the 'interconnects' property to Adreno SMMU nodes only (qcom,adreno-smmu with qcom,qcs615-smmu-500, qcom,qcs8300-smmu-500, qcom,sa8775p-smmu-500 or qcom,sc7280-smmu-500 compatible), so non-Adreno SMMU nodes on the same SoC cannot use this property. - Added DTS patches for kodiak, lemans, monaco and talos to add the GEM_NOC interconnect path for the adreno_smmu node on each platform. Link to v1: https://lore.kernel.org/all/20260516-smmu_interconnect_addition-v1-0-f889d933f5c1@oss.qualcomm.com/ Signed-off-by: Bibek Kumar Patro --- Bibek Kumar Patro (6): dt-bindings: iommu: arm,smmu: Document interconnects property iommu/arm-smmu: Add interconnect bandwidth voting support arm64: dts: qcom: kodiak: Add GEM_NOC interconnect for adreno SMMU arm64: dts: qcom: lemans: Add GEM_NOC interconnect for adreno SMMU arm64: dts: qcom: monaco: Add GEM_NOC interconnect for adreno SMMU arm64: dts: qcom: talos: Add GEM_NOC interconnect for adreno SMMU .../devicetree/bindings/iommu/arm,smmu.yaml | 27 ++++++++++ arch/arm64/boot/dts/qcom/kodiak.dtsi | 2 + arch/arm64/boot/dts/qcom/lemans.dtsi | 2 + arch/arm64/boot/dts/qcom/monaco.dtsi | 2 + arch/arm64/boot/dts/qcom/talos.dtsi | 2 + drivers/iommu/arm/arm-smmu/arm-smmu.c | 57 +++++++++++++++++++++- drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 + 7 files changed, 92 insertions(+), 2 deletions(-) --- base-commit: c1ecb239fa3456529a32255359fc78b69eb9d847 change-id: 20260516-smmu_interconnect_addition-d9567535e9d7 Best regards, -- Bibek Kumar Patro