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a=ed25519-sha256; t=1779806527; l=5501; i=bibek.patro@oss.qualcomm.com; s=20260408; h=from:subject:message-id; bh=enf3+ZPlPMPCTgLbtus14tXkNZXCGM3zYc7lLFmNwZ8=; b=5d3nHDhy04hWjF4+t0oXqcQisvn2D3hkiltQR8u/D4ZOaNXWUXZ+Dx8dm99JGymfCvg4snhA9 /S+Tl5jz0SfBV0ZP6FN8x/4AJYqKmyAf4mKOb2z1v7X32OMPgJFAoJo X-Developer-Key: i=bibek.patro@oss.qualcomm.com; a=ed25519; pk=V4oTa+TgRi7dib76fc92V+rslyRCAKbK8D4b2RVsMbc= X-Proofpoint-GUID: U9JrfDwTnbMaItuFpeUnzBKVfo8caTLq X-Authority-Analysis: v=2.4 cv=TZ+mcxQh c=1 sm=1 tr=0 ts=6a15b14e cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=taUV0mOn9u7JAoyayg0A:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-ORIG-GUID: U9JrfDwTnbMaItuFpeUnzBKVfo8caTLq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI2MDEyNiBTYWx0ZWRfX+CIzEOLAZ7zi kothikF4ih8tYdk3A1apbsm25yDhcOuq1EYVtyq/WCwtrrwERnvSDsfODi6S/FAOCziv3ruJ8WM hrkL4Sho0O+ITb8vaZ/fUusHt91x7N0L8MO82+n+syvHyHLDK/uPkyG0i0bqxylT0EeTa471qFy 2hIMQPVJIemuYJy4IG57gvFGup76cr6eUsGL8pNoLs32Vu1XZu7XoQ+nnPR/fE/agUsqmaaAoHb CTksDbbiWsLoQlDsLGDeXIJTKxNWufAP8mvRevCOoYZfa/30IH0joGBJufsObXT9Rl/djFM4zK9 xq582pAxd7fAM9b7GV6jp6nQKM8mP8AF9CbOVn9vxLwSrFbSGYtebFBNILEvNlfgYg79jZXsLs0 05AW6c8PE/eVgEC3c+XRgEypHWraUomu6xpKapFyIEdvwpw3quHjtZUsfWawNpZRv/2qWpKmIkn godf5tnxuEB+qBRswlQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-26_03,2026-05-26_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 adultscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605260126 On some SoCs the SMMU registers require an active interconnect bandwidth vote to be accessible. While other clients typically satisfy this requirement implicitly, certain corner cases (e.g. during sleep/wakeup transitions) can leave the SMMU without a vote, causing intermittent register access failures. Add support for an optional interconnect path to the arm-smmu driver and vote for bandwidth while the SMMU is active. The path is acquired from DT if present and ignored otherwise. The bandwidth vote is enabled before accessing SMMU registers during probe and runtime resume, and released during runtime suspend and on error paths. Generally, from an architectural perspective, GEM_NOC and DDR are expected to have an active vote whenever the adreno_smmu block is powered on. In most common use cases, this requirement is implicitly satisfied because other GPU-related clients (for example, the GMU device) already hold a GEM_NOC vote when adreno_smmu is enabled. However, there are certain corner cases, such as during sleep/wakeup transitions, where the GEM_NOC vote can be removed before adreno_smmu is powered down. If adreno_smmu is then accessed while the interconnect vote is missing, it can lead to the observed failures. Because of the precise ordering involved, this scenario is difficult to reproduce consistently. (also GDSC is involved in adreno usecases can have an independent vote) Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 57 +++++++++++++++++++++++++++++++++-- drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++ 2 files changed, 57 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 0bd21d206eb3e75c3b9fb1364cdc92e82c5aa499..07c7e44ec6a5bd1488f00f87d859a20495e46601 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -53,6 +53,11 @@ #define MSI_IOVA_BASE 0x8000000 #define MSI_IOVA_LENGTH 0x100000 +/* Interconnect bandwidth vote values for the SMMU register access path */ +#define ARM_SMMU_ICC_AVG_BW 0 +#define ARM_SMMU_ICC_PEAK_BW_HIGH 1000 +#define ARM_SMMU_ICC_PEAK_BW_LOW 0 + static int force_stage; module_param(force_stage, int, S_IRUGO); MODULE_PARM_DESC(force_stage, @@ -86,6 +91,36 @@ static inline void arm_smmu_rpm_put(struct arm_smmu_device *smmu) } } +static int arm_smmu_icc_get(struct arm_smmu_device *smmu) +{ + smmu->icc_path = devm_of_icc_get(smmu->dev, NULL); + if (IS_ERR(smmu->icc_path)) { + int err = PTR_ERR(smmu->icc_path); + + if (err == -ENODEV) { + smmu->icc_path = NULL; + return 0; + } + return dev_err_probe(smmu->dev, err, + "failed to get interconnect path\n"); + } + return 0; +} + +static void arm_smmu_icc_enable(struct arm_smmu_device *smmu) +{ + if (smmu->icc_path) + WARN_ON(icc_set_bw(smmu->icc_path, ARM_SMMU_ICC_AVG_BW, + ARM_SMMU_ICC_PEAK_BW_HIGH)); +} + +static void arm_smmu_icc_disable(struct arm_smmu_device *smmu) +{ + if (smmu->icc_path) + WARN_ON(icc_set_bw(smmu->icc_path, ARM_SMMU_ICC_AVG_BW, + ARM_SMMU_ICC_PEAK_BW_LOW)); +} + static void arm_smmu_rpm_use_autosuspend(struct arm_smmu_device *smmu) { /* @@ -2189,6 +2224,17 @@ static int arm_smmu_device_probe(struct platform_device *pdev) if (err) return err; + /* + * Acquire and vote the interconnect path before accessing any SMMU + * registers (including ARM_SMMU_GR0_ID0 in arm_smmu_device_cfg_probe). + */ + err = arm_smmu_icc_get(smmu); + if (err) { + clk_bulk_disable_unprepare(smmu->num_clks, smmu->clks); + return err; + } + arm_smmu_icc_enable(smmu); + err = arm_smmu_device_cfg_probe(smmu); if (err) return err; @@ -2273,8 +2319,10 @@ static void arm_smmu_device_shutdown(struct platform_device *pdev) if (pm_runtime_enabled(smmu->dev)) pm_runtime_force_suspend(smmu->dev); - else + else { clk_bulk_disable(smmu->num_clks, smmu->clks); + arm_smmu_icc_disable(smmu); + } clk_bulk_unprepare(smmu->num_clks, smmu->clks); } @@ -2294,9 +2342,13 @@ static int __maybe_unused arm_smmu_runtime_resume(struct device *dev) struct arm_smmu_device *smmu = dev_get_drvdata(dev); int ret; + arm_smmu_icc_enable(smmu); + ret = clk_bulk_enable(smmu->num_clks, smmu->clks); - if (ret) + if (ret) { + arm_smmu_icc_disable(smmu); return ret; + } arm_smmu_device_reset(smmu); @@ -2308,6 +2360,7 @@ static int __maybe_unused arm_smmu_runtime_suspend(struct device *dev) struct arm_smmu_device *smmu = dev_get_drvdata(dev); clk_bulk_disable(smmu->num_clks, smmu->clks); + arm_smmu_icc_disable(smmu); return 0; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 26d2e33cd328b8278888585fc07a31485d9397e2..c00606a416b2f4bb44a35e5d67f6ef801df68e1c 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -335,6 +336,7 @@ struct arm_smmu_device { int num_clks; unsigned int *irqs; struct clk_bulk_data *clks; + struct icc_path *icc_path; spinlock_t global_sync_lock; -- 2.34.1