From: Richard Cheng <icheng@nvidia.com>
To: tony.luck@intel.com
Cc: reinette.chatre@intel.com, shuah@kernel.org, Dave.Martin@arm.com,
james.morse@arm.com, babu.moger@amd.com,
linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org,
fenghuay@nvidia.com, newtonl@nvidia.com, kristinc@nvidia.com,
kaihengf@nvidia.com, kobak@nvidia.com,
Richard Cheng <icheng@nvidia.com>
Subject: [PATCH] selftests/resctrl: Implement cl_flush() and sb() on aarch64
Date: Tue, 26 May 2026 10:44:05 +0800 [thread overview]
Message-ID: <20260526024405.7979-1-icheng@nvidia.com> (raw)
cl_flush() and sb() only works for i386 and x86_64 in fill_buf.c, so on
aarch64 both compile to empty function. mem_flush() walks the buffer
calling no-op cl_flush() per cache line and finishes with a no-op sb(),
leaving any caller that expects a flushed buffer, e.g. CMT, L3_CAT
operating on unflushed state with no warning.
Add code block for aarch64 using the ARM equivalents
* "dc civac, %0" for cl_flush()
* "dsb sy" for sb()
Both are EL0-accessible on Linux aarch64.
Signed-off-by: Richard Cheng <icheng@nvidia.com>
---
tools/testing/selftests/resctrl/fill_buf.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/tools/testing/selftests/resctrl/fill_buf.c b/tools/testing/selftests/resctrl/fill_buf.c
index 19a01a52dc1a..a41d21e5a64e 100644
--- a/tools/testing/selftests/resctrl/fill_buf.c
+++ b/tools/testing/selftests/resctrl/fill_buf.c
@@ -27,6 +27,9 @@ static void sb(void)
#if defined(__i386) || defined(__x86_64)
asm volatile("sfence\n\t"
: : : "memory");
+#elif defined(__aarch64__)
+ asm volatile("dsb sy\n\t"
+ : : : "memory");
#endif
}
@@ -35,6 +38,9 @@ static void cl_flush(void *p)
#if defined(__i386) || defined(__x86_64)
asm volatile("clflush (%0)\n\t"
: : "r"(p) : "memory");
+#elif defined(__aarch64__)
+ asm volatile("dc civac, %0\n\t"
+ : : "r"(p) : "memory");
#endif
}
--
2.43.0
reply other threads:[~2026-05-26 2:44 UTC|newest]
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