From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBE963CF68E; Tue, 26 May 2026 08:48:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779785333; cv=none; b=XgV45UehsImvTi5RftHCdBOs95dLSc4tXJV5HlzkSsfiGzIpXM/ccb+smaeTS6pGMr62IaljT+4gKOdJqJUInyMkD5qMwWERGWmUXiN/2BudPhRPzSbOCDasL4Xo2N7o3z4QRvHzLEm9pVo4s+M0RX1Z8O4MB9RznLniZNKF1DA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779785333; c=relaxed/simple; bh=yvgeFKF1lxj68nJj1F02veizJ6oL6zjIexlKwl/89nE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FRDbiS/GqY3XwRbe9PVl9Yg6YffDHDbeEqQS4Vci7ghAy3RMr78LKxDBXb8BLbaOfk4RwuEu3aQAujXWG9YaHiPT7OP4pRZR4VwJs4T8c51OsvthgTgrBKdlkJN/NZlUEb0iwv+aQUiMz4WXt9hZ15+NQXutIbchsd/sXX6R5O0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FlIcJAhB; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FlIcJAhB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DA04D1F00A3A; Tue, 26 May 2026 08:48:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779785331; bh=ZkizuxwMrkjBcE6tO2uEvys7AHOh8iY86fCmxYrdhW4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=FlIcJAhB4+HPCjoi2v1/DWzFXkx5SwED2Rosdo3T5qVCvOlBmD9PDmZTBLAJleYtv nJPOYWcfQ1wux0m68qnLrPHCTSqIsE2uI197krmPc2bQzxjCrPIDzUk7tJz5F8ZbTh pEQDgdigmKI/WMg2RuG/wPgWakGjhvT/ST6cQbSsJwzkb+jxglAgNpcsAv7PN0FyjW Yp6OFrsolUQRB5A5uT9wMxJnGBIdH6fVBuNsS4SsI3DisO7xyqU8OxCjzAw52prUNk m4KqkOSEZ1Cgrh2tDUUUA4h4wnHf5E3q+OVYbI9f1H+RXj+VPW2aKyHyZT9iZLTBtO BKiw8EAI4OS/g== From: Claudiu Beznea To: vkoul@kernel.org, Frank.Li@kernel.org, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, p.zabel@pengutronix.de, geert+renesas@glider.be, kuninori.morimoto.gx@renesas.com, long.luu.ur@renesas.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea , John Madieu Subject: [PATCH v6 18/18] dmaengine: sh: rz-dmac: Set the Link End (LE) bit on the last descriptor Date: Tue, 26 May 2026 11:47:10 +0300 Message-ID: <20260526084710.3491480-19-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260526084710.3491480-1-claudiu.beznea@kernel.org> References: <20260526084710.3491480-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Claudiu Beznea On an RZ/G2L-based system, it has been observed that when the DMA channels for all enabled IPs are active (TX and RX for one serial IP, TX and RX for one audio IP, and TX and RX for one SPI IP), shortly after all of them are started, the system can become irrecoverably blocked. In one debug session the system did not block, and the DMA HW registers were inspected. It was found that the DER (Descriptor Error) bit in the CHSTAT register for one of the SPI DMA channels was set. According to the RZ/G2L HW Manual, Rev. 1.30, chapter 14.4.7 Channel Status Register n/nS (CHSTAT_n/nS), description of the DER bit, the DER bit is set when the LV (Link Valid) value loaded with a descriptor in link mode is 0. This means that the DMA engine has loaded an invalid descriptor (as defined in Table 14.14, Header Area, of the same manual). The same chapter states that when a descriptor error occurs, the transfer is stopped, but no DMA error interrupt is generated. Set the LE bit on the last descriptor of a transfer. This informs the DMA engine that this is the final descriptor for the transfer. Tested-by: John Madieu Signed-off-by: Claudiu Beznea --- Changes in v6: - collected tags Changes in v5: - none Changes in v4: - none Changes in v3: - none Changes in v2: - none drivers/dma/sh/rz-dmac.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 2a7124e4aea3..f1174d25da84 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -200,6 +200,7 @@ struct rz_dmac { /* LINK MODE DESCRIPTOR */ #define HEADER_LV BIT(0) +#define HEADER_LE BIT(1) #define HEADER_WBD BIT(2) #define RZ_DMAC_MAX_CHAN_DESCRIPTORS 16 @@ -382,7 +383,7 @@ static void rz_dmac_prepare_desc_for_memcpy(struct rz_dmac_chan *channel) lmdesc->chcfg = chcfg; lmdesc->chitvl = 0; lmdesc->chext = 0; - lmdesc->header = HEADER_LV; + lmdesc->header = HEADER_LV | HEADER_LE; rz_dmac_set_dma_req_no(dmac, channel->index, dmac->info->default_dma_req_no); @@ -425,7 +426,7 @@ static void rz_dmac_prepare_descs_for_slave_sg(struct rz_dmac_chan *channel) lmdesc->chext = 0; if (i == (sg_len - 1)) { lmdesc->chcfg = (channel->chcfg & ~CHCFG_DEM); - lmdesc->header = HEADER_LV; + lmdesc->header = HEADER_LV | HEADER_LE; } else { lmdesc->chcfg = channel->chcfg; lmdesc->header = HEADER_LV; -- 2.43.0