From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A10DB3F39EA; Wed, 27 May 2026 11:08:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779880098; cv=none; b=PTd98bJXt7Xxlgr1HUL5Fcdh/VOth1dko4wfOKb7iPKEbqrW44tbiNmONhDfJrKP8bLq0hLMlXrS28SBumr6cZvGvvAguQJW5meY+FOEh1/5CBPav52KjWSR/lIIkcj2PdJIHaBkajf4tkJ8jyHIdnAuF2u/8IdgmzLfqRK3ylc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779880098; c=relaxed/simple; bh=ReiDdwkcSLe/Nn2wIdWLLJpIXqoldTX9ysS+Ik/I7zA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=HNByagAPiuiYq04/jRUo+ZXgevzhjG4HiGmQvFeDSnvXhCvXvze0fEK+Xebax/IeSzPzCt8GP7zvjlIQWw2RM0Yh/A7FRWBtTZW+gKuegiiGEqjXAeore1/9KsmTDFrPLI9kaoTFLeZ6qBjECLJI3aMjycSu1PvqNqzIVoafot8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=jh3KTMZk; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="jh3KTMZk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1779880098; x=1811416098; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=ReiDdwkcSLe/Nn2wIdWLLJpIXqoldTX9ysS+Ik/I7zA=; b=jh3KTMZk3rLwTlk7IlxADdHm25NgZjHLSHV4YfP4O2SUw0FOT+p25alz aONPNZq3LKKCBjn4UoM40C20cY8JTBP/lve65h0u7D1IFk7/9dWL/Y8+G qtYB6oGnj4Uvyh2maYFxd0drFhAgEPzGo4d8b3qNGocbF/4qoMMUQ7TXg RwneBYPHEvnznjuVhM/w2absvCQ/e2sLLCbcJ17Y7uMumDA90EhFVd9CY YbEyibate0XUMcZ3lasdjjNoPa4fuXAlhg+Arxvupxx5jvhsKk0lD57Ma SosYog3sb8KmvCoG1pPFRTqLwb+qFZRDaH0PeiwuJBkShT8dOTZxO6G85 g==; X-CSE-ConnectionGUID: YtkCLYPYRH+rVljlFN//UA== X-CSE-MsgGUID: zq6Q3617RFqRIFdRKtuy8A== X-IronPort-AV: E=Sophos;i="6.24,171,1774335600"; d="scan'208";a="58112124" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2026 04:08:17 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.41; Wed, 27 May 2026 04:08:16 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 27 May 2026 04:08:12 -0700 From: Balakrishnan Sambath Date: Wed, 27 May 2026 16:37:28 +0530 Subject: [PATCH v5 12/12] media: microchip-isc: scale DPC black level to sensor bit depth Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260527-microchip-isc-fixes-v5-12-b0ec1bb954be@microchip.com> References: <20260527-microchip-isc-fixes-v5-0-b0ec1bb954be@microchip.com> In-Reply-To: <20260527-microchip-isc-fixes-v5-0-b0ec1bb954be@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: Laurent Pinchart , Kieran Bingham , Sakari Ailus , Balamanikandan Gunasundar , , , , "Balakrishnan Sambath" X-Mailer: b4 0.14.3 The DPC_BLCFG black level register expects counts in the sensor's native bit depth. The previous fixed 10-bit value (64 counts) under- corrects 12-bit sensors and over-corrects 8-bit ones, producing an incorrect black point. Scale the nominal 10-bit value to match the 8/10/12-bit sensor bus width derived from pfe_cfg0_bps. Co-developed-by: Balamanikandan Gunasundar Signed-off-by: Balamanikandan Gunasundar Signed-off-by: Balakrishnan Sambath --- .../media/platform/microchip/microchip-sama7g5-isc.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/microchip/microchip-sama7g5-isc.c b/drivers/media/platform/microchip/microchip-sama7g5-isc.c index f51c7cac25df..067a6e1558d3 100644 --- a/drivers/media/platform/microchip/microchip-sama7g5-isc.c +++ b/drivers/media/platform/microchip/microchip-sama7g5-isc.c @@ -26,6 +26,7 @@ * HIS: Histogram module performs statistic counters on the frames */ +#include #include #include #include @@ -289,9 +290,25 @@ static void isc_sama7g5_config_dpc(struct isc_device *isc) { u32 bay_cfg = isc->config.sd_format->cfa_baycfg; struct regmap *regmap = isc->regmap; + u32 bps, bloff; + + /* + * Scale the nominal 10-bit black level offset (64 counts) to the + * actual sensor bus width. + * ISC_PFE_CFG0_BPS encodes (12 - bit_depth) / 2 in bits[30:28]: + * BPS_EIGHT = 4 -> 8-bit -> bloff = 64 >> 2 = 16 + * BPS_TEN = 2 -> 10-bit -> bloff = 64 + * BPS_TWELVE = 0 -> 12-bit -> bloff = min(64 << 2, 255) = 255 + * The BLOFF hardware field is 8-bit so values are clamped to 255. + */ + bps = FIELD_GET(ISC_PFE_CFG0_BPS_MASK, isc->config.sd_format->pfe_cfg0_bps); + if (bps >= 2) + bloff = 64u >> (bps - 2); + else + bloff = min(64u << (2 - bps), 255u); regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BLOFF_MASK, - (64 << ISC_DPC_CFG_BLOFF_SHIFT)); + (bloff << ISC_DPC_CFG_BLOFF_SHIFT)); regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BAYCFG_MASK, (bay_cfg << ISC_DPC_CFG_BAYCFG_SHIFT)); } -- 2.34.1