From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD4FD3F4111; Wed, 27 May 2026 11:07:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779880054; cv=none; b=vAU2Rxlfpvv/AVaFh7rbVtp99dVtYYsLmRZxQVAo41866pzjAPrUnLu4w1n9Qt/JxbaPy6lRMg7LVVO2zoKMLMz2qe/J4+Phuu+CInzIlv6eVJGs90BEX62GGuXjDv6dVCV8tIc8lT1KWHPbklr+6hTaHKNEhzPheXXdjcM9AfE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779880054; c=relaxed/simple; bh=gvdrgbWAjTx1CGi+PD6csR2l/AwBIyyRN8PqO/RwaYE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=L5igZyvxWs3VNu5GchLLkSDv1E0r3XNF7MS6qonhuspv6nhhtA+tpaiRJGCBSgXZBVV3PbrunUkyjhf/BEatOMlLtdUk/R33cFOF7yP45Cuepwan3u1wGY/XErJP2EYh9XGCZm7sSlpaLPrHGMZk9lg7mqku1FxV3j6vj3Q2hEg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=WoU41Uo0; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="WoU41Uo0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1779880052; x=1811416052; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=gvdrgbWAjTx1CGi+PD6csR2l/AwBIyyRN8PqO/RwaYE=; b=WoU41Uo0wX2RJ3HKnowbc3o3WVlO3iRk8vZ+iRnzhiK43F6eG5wWPriM a/KiC2/nB/g7PmLKYWiG2q74WRLH7oMJfAR9DvAbaCs+vJsXISoB1lTFu jn0qVSGyg/1TpM4uO6EPXTQp22x+a381No6to7BB8QjlO4dr/HdBUri/b g99OmtUROawqWChwUzywVDrucz++E/YtYSYFQmsJiwItl++e+I4EQDAz/ OZMxwE4kTjIeGG6kxQ4RP0ENOVDwdqUYybk5zSRD2ovbdVGE3/rde/2Xm s6eyRhS1uLpfZLMAedagVUziKkj9XwDjObhuKWC5CKNXjIbrRemz03aOF w==; X-CSE-ConnectionGUID: 0DJN6ARWQbmuWsxbhB66lA== X-CSE-MsgGUID: ghkaf6t8SkqkKEMPqifvQA== X-IronPort-AV: E=Sophos;i="6.24,171,1774335600"; d="scan'208";a="225356274" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2026 04:07:31 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.41; Wed, 27 May 2026 04:07:31 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 27 May 2026 04:07:27 -0700 From: Balakrishnan Sambath Date: Wed, 27 May 2026 16:37:18 +0530 Subject: [PATCH v5 02/12] media: microchip-isc: fix WB offset and gain register field masking Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260527-microchip-isc-fixes-v5-2-b0ec1bb954be@microchip.com> References: <20260527-microchip-isc-fixes-v5-0-b0ec1bb954be@microchip.com> In-Reply-To: <20260527-microchip-isc-fixes-v5-0-b0ec1bb954be@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: Laurent Pinchart , Kieran Bingham , Sakari Ailus , Balamanikandan Gunasundar , , , , "Balakrishnan Sambath" X-Mailer: b4 0.14.3 ISC_WB_O_* and ISC_WB_G_* pack two 13-bit fields per register. Sign extension from negative offsets corrupts the upper field. Mask both fields to 13 bits before packing. Fixes: 91b4e487b0c6 ("media: microchip: add ISC driver as Microchip ISC") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath --- .../media/platform/microchip/microchip-isc-base.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/drivers/media/platform/microchip/microchip-isc-base.c index a7cdc743fda7..45b94f1e89d8 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -61,18 +61,23 @@ static inline void isc_update_awb_ctrls(struct isc_device *isc) /* In here we set our actual hw pipeline config */ + /* + * Mask offset fields to 13 bits. Sign extension of negative s32 + * values would otherwise corrupt the adjacent field. + */ regmap_write(isc->regmap, ISC_WB_O_RGR, - ((ctrls->offset[ISC_HIS_CFG_MODE_R])) | - ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16)); + ((u32)ctrls->offset[ISC_HIS_CFG_MODE_R] & GENMASK(12, 0)) | + (((u32)ctrls->offset[ISC_HIS_CFG_MODE_GR] & GENMASK(12, 0)) << 16)); regmap_write(isc->regmap, ISC_WB_O_BGB, - ((ctrls->offset[ISC_HIS_CFG_MODE_B])) | - ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16)); + ((u32)ctrls->offset[ISC_HIS_CFG_MODE_B] & GENMASK(12, 0)) | + (((u32)ctrls->offset[ISC_HIS_CFG_MODE_GB] & GENMASK(12, 0)) << 16)); + /* Gains are 13-bit unsigned fields [12:0] and [28:16] */ regmap_write(isc->regmap, ISC_WB_G_RGR, - ctrls->gain[ISC_HIS_CFG_MODE_R] | - (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16)); + (ctrls->gain[ISC_HIS_CFG_MODE_R] & GENMASK(12, 0)) | + ((ctrls->gain[ISC_HIS_CFG_MODE_GR] & GENMASK(12, 0)) << 16)); regmap_write(isc->regmap, ISC_WB_G_BGB, - ctrls->gain[ISC_HIS_CFG_MODE_B] | - (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16)); + (ctrls->gain[ISC_HIS_CFG_MODE_B] & GENMASK(12, 0)) | + ((ctrls->gain[ISC_HIS_CFG_MODE_GB] & GENMASK(12, 0)) << 16)); } static inline void isc_reset_awb_ctrls(struct isc_device *isc) -- 2.34.1