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Miller" , Eric Dumazet , Paolo Abeni , Jiawen Wu , Mengyuan Lou , Heiner Kallweit , Russell King , Mohsin Bashir , Kees Cook , Andrew Lunn Cc: mike.marciniszyn@gmail.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v3 3/4] net: pcs: xpcs: Add hooks for xpcs configuration of rsfec Date: Tue, 26 May 2026 20:09:57 -0400 Message-ID: <20260527000958.81108-4-mike.marciniszyn@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260527000958.81108-1-mike.marciniszyn@gmail.com> References: <20260527000958.81108-1-mike.marciniszyn@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: "Mike Marciniszyn (Meta)" The DW PCS IP data sheet calls out the need to populate these vendor registers when operating at speeds above 10Gbps. This change enables the correct FEC settings to enable RS-FEC encoding on the link which is the standard used for most links at these higher speeds. Reviewed-by: Alexander Duyck Signed-off-by: Mike Marciniszyn (Meta) --- v3: - lanes -> channels - Added 50gbaser2 that was missing - remove auto probe for addr 0/1 - call xpcs_mdev_write_ch() - reformat building devs1 mask in xpcs_get_pma_mmd() v2: https://lore.kernel.org/netdev/20260511182604.1338-2-mike.marciniszyn@gmail.com/ - Allow mdiobus probing for addr 0 and addr 1 - Add xpcs_find* helpers based on phy_find* to avoid hardcoded addresses - Remove xpcs_bus write and use mdiodev_c45_write instead - Address comment on use of MDIO_PMA_RSFEC_CTRL v1: https://lore.kernel.org/all/20260506190904.4029-2-mike.marciniszyn@gmail.com/ drivers/net/pcs/pcs-xpcs.c | 88 ++++++++++++++++++++++++++++++++++++++ drivers/net/pcs/pcs-xpcs.h | 6 +++ include/uapi/linux/mdio.h | 3 ++ 3 files changed, 97 insertions(+) diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index d59ba99c3764..342d1cc2adbc 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -1408,6 +1408,90 @@ static int xpcs_read_ids(struct dw_xpcs *xpcs) return 0; } +static int xpcs_get_pma_mmd(struct dw_xpcs *xpcs) +{ + int devs1, b; + + devs1 = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVS1); + if (devs1 < 0) + return devs1; + + /* Locate the PMA closest to the PCS as this should be the one provided + * with the DW IP. This is identified by being the PMA with the + * highest MMD device address. + */ + devs1 &= MDIO_DEVS_SEP_PMA1 | MDIO_DEVS_SEP_PMA2 | + MDIO_DEVS_SEP_PMA3 | MDIO_DEVS_SEP_PMA4 | + MDIO_DEVS_PMAPMD; + b = fls(devs1); + if (b) + return b - 1; + + return -ENODEV; +} + +struct pma_pcs_values { + int channels; + u16 rsfec_ctrl; +}; + +static int +xpcs_config_rsfec_pma(struct dw_xpcs *xpcs, const struct pma_pcs_values *v) +{ + int ret = 0, i, pma_mmd; + + pma_mmd = xpcs_get_pma_mmd(xpcs); + if (pma_mmd < 1) + return pma_mmd; + + for (i = 0; ret >= 0 && i < v->channels; i++) { + ret = xpcs_mdev_write_ch(xpcs, i, pma_mmd, + MDIO_PMA_RSFEC_CTRL, v->rsfec_ctrl); + } + + return ret; +} + +static int xpcs_25gbaser_pma_config(struct dw_xpcs *xpcs) +{ + const struct pma_pcs_values v = { + .rsfec_ctrl = 0, + .channels = 1, + }; + + return xpcs_config_rsfec_pma(xpcs, &v); +} + +static int xpcs_50gbaser_pma_config(struct dw_xpcs *xpcs) +{ + const struct pma_pcs_values v = { + .rsfec_ctrl = DW_VR_RSFEC_CTRL_TC_PAD_ALTER, + .channels = 1, + }; + + return xpcs_config_rsfec_pma(xpcs, &v); +} + +static int xpcs_50gbaser2_pma_config(struct dw_xpcs *xpcs) +{ + const struct pma_pcs_values v = { + .rsfec_ctrl = DW_VR_RSFEC_CTRL_TC_PAD_ALTER, + .channels = 2, + }; + + return xpcs_config_rsfec_pma(xpcs, &v); +} + +static int xpcs_100gbasep_pma_config(struct dw_xpcs *xpcs) +{ + const struct pma_pcs_values v = { + .rsfec_ctrl = MDIO_PMA_RSFEC_CTRL_4LANE_PMD, + .channels = 2, + }; + + return xpcs_config_rsfec_pma(xpcs, &v); +} + static const struct dw_xpcs_compat synopsys_xpcs_compat[] = { { .interface = PHY_INTERFACE_MODE_USXGMII, @@ -1421,6 +1505,7 @@ static const struct dw_xpcs_compat synopsys_xpcs_compat[] = { .interface = PHY_INTERFACE_MODE_25GBASER, .supported = xpcs_25gbaser_features, .an_mode = DW_AN_C73, + .pma_config = xpcs_25gbaser_pma_config, }, { .interface = PHY_INTERFACE_MODE_XLGMII, .supported = xpcs_xlgmii_features, @@ -1429,14 +1514,17 @@ static const struct dw_xpcs_compat synopsys_xpcs_compat[] = { .interface = PHY_INTERFACE_MODE_50GBASER, .supported = xpcs_50gbaser_features, .an_mode = DW_AN_C73, + .pma_config = xpcs_50gbaser_pma_config, }, { .interface = PHY_INTERFACE_MODE_LAUI, .supported = xpcs_50gbaser2_features, .an_mode = DW_AN_C73, + .pma_config = xpcs_50gbaser2_pma_config, }, { .interface = PHY_INTERFACE_MODE_100GBASEP, .supported = xpcs_100gbasep_features, .an_mode = DW_AN_C73, + .pma_config = xpcs_100gbasep_pma_config, }, { .interface = PHY_INTERFACE_MODE_10GBASER, .supported = xpcs_10gbaser_features, diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h index 36f4906e689a..ab47d6dd050c 100644 --- a/drivers/net/pcs/pcs-xpcs.h +++ b/drivers/net/pcs/pcs-xpcs.h @@ -94,6 +94,12 @@ #define DW_VR_MII_DIG_CTRL2_TX_POL_INV BIT(4) #define DW_VR_MII_DIG_CTRL2_RX_POL_INV BIT(0) +/* Clause 133 defines */ +/* RSFEC transcode pad alter + * DW vendor extension in RS-FEC control + */ +#define DW_VR_RSFEC_CTRL_TC_PAD_ALTER BIT(10) + #define DW_XPCS_INFO_DECLARE(_name, _pcs, _pma) \ static const struct dw_xpcs_info _name = { .pcs = _pcs, .pma = _pma } diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h index b2541c948fc1..5219c877b2cf 100644 --- a/include/uapi/linux/mdio.h +++ b/include/uapi/linux/mdio.h @@ -317,6 +317,9 @@ #define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */ #define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */ +/* RSFEC PMA Control register */ +#define MDIO_PMA_RSFEC_CTRL_4LANE_PMD BIT(3) + /* PMA 10GBASE-R Fast Retrain status and control register. */ #define MDIO_PMA_10GBR_FSRT_ENABLE 0x0001 /* Fast retrain enable */ -- 2.43.0