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Wed, 27 May 2026 02:54:33 -0700 (PDT) Received: from hu-mojha-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-841d70f17cbsm1809325b3a.45.2026.05.27.02.54.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2026 02:54:33 -0700 (PDT) From: Mukesh Ojha To: Thomas Gleixner Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Mukesh Ojha , Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v2 1/4] irqchip/qcom-pdc: Split __pdc_enable_intr() into per-version helpers Date: Wed, 27 May 2026 15:24:23 +0530 Message-ID: <20260527095426.2324504-2-mukesh.ojha@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260527095426.2324504-1-mukesh.ojha@oss.qualcomm.com> References: <20260527095426.2324504-1-mukesh.ojha@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=ONEXGyaB c=1 sm=1 tr=0 ts=6a16bf68 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=eikPim43zSuFQStimlMA:9 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-ORIG-GUID: 4ychBpefPeHEv-VUOM_xTFBFbsGI8apj X-Proofpoint-GUID: 4ychBpefPeHEv-VUOM_xTFBFbsGI8apj X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI3MDA5NSBTYWx0ZWRfXzLnQ5s4cDd0o CH+OOQMSFARDBRWsz4PSDj600Bl3xSr/XwLfF0lo9DSXniOHNtUYG0dBvKuoXgap1O9W6hRRGI5 uxtX8vbE1BiV6C/TEYkN84VlPn58u2n8XG9wyagkm7kZTqPvtsnsPefyQYniaUtjGLOkcYXgyHe RYowjnMUrQQpINRCxjYZHqJYY25BZ2WqEu6lr7qhv/pm9AKgfja00DXrUIAjjWk35C5ol80PzGA TPtai5aBheXnuVtAeW1jpjoGihMAGOdOOtLFee7pbrfAWS6/HQvjs5Ok6Qvi4br8n+P2ht9GweQ wzGZu/GWbmji0iuxjMLyDBg7aWnWXPa62vxUIbPQ+dLkcyFrlqsVojY7jPyxLykcGYO2snlLwNV cnbjFmfnbb6iHasXYGHNQRvpVvXzA0dejkYOkZ/UbR+I3z1NVly3kRPLMYf4QPjh47w8rM66ofs UaHPqoM0FRG1ue6F5Eg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-27_01,2026-05-26_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 suspectscore=0 impostorscore=0 adultscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605270095 The __pdc_enable_intr() function contains a version branch that selects between two distinct enable mechanisms: a bank-based IRQ_ENABLE_BANK register for HW < 3.2, and a per-pin enable bit in IRQ_i_CFG for HW >= 3.2. These two paths share no code and serve different hardware. Split them into two focused static functions: pdc_enable_intr_bank() for HW < 3.2 and pdc_enable_intr_cfg() for HW >= 3.2. No functional change. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha --- drivers/irqchip/qcom-pdc.c | 42 +++++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 16 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 32b77fa93f73..a72e32896e64 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -97,28 +97,38 @@ static void pdc_x1e_irq_enable_write(u32 bank, u32 enable) pdc_base_reg_write(base, IRQ_ENABLE_BANK, bank, enable); } -static void __pdc_enable_intr(int pin_out, bool on) +static void pdc_enable_intr_bank(int pin_out, bool on) { unsigned long enable; + u32 index, mask; - if (pdc_version < PDC_VERSION_3_2) { - u32 index, mask; + index = pin_out / 32; + mask = pin_out % 32; - index = pin_out / 32; - mask = pin_out % 32; + enable = pdc_reg_read(IRQ_ENABLE_BANK, index); + __assign_bit(mask, &enable, on); - enable = pdc_reg_read(IRQ_ENABLE_BANK, index); - __assign_bit(mask, &enable, on); + if (pdc_x1e_quirk) + pdc_x1e_irq_enable_write(index, enable); + else + pdc_reg_write(IRQ_ENABLE_BANK, index, enable); +} - if (pdc_x1e_quirk) - pdc_x1e_irq_enable_write(index, enable); - else - pdc_reg_write(IRQ_ENABLE_BANK, index, enable); - } else { - enable = pdc_reg_read(IRQ_i_CFG, pin_out); - __assign_bit(IRQ_i_CFG_IRQ_ENABLE, &enable, on); - pdc_reg_write(IRQ_i_CFG, pin_out, enable); - } +static void pdc_enable_intr_cfg(int pin_out, bool on) +{ + unsigned long enable; + + enable = pdc_reg_read(IRQ_i_CFG, pin_out); + __assign_bit(IRQ_i_CFG_IRQ_ENABLE, &enable, on); + pdc_reg_write(IRQ_i_CFG, pin_out, enable); +} + +static void __pdc_enable_intr(int pin_out, bool on) +{ + if (pdc_version < PDC_VERSION_3_2) + pdc_enable_intr_bank(pin_out, on); + else + pdc_enable_intr_cfg(pin_out, on); } static void pdc_enable_intr(struct irq_data *d, bool on) -- 2.53.0