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[72.90.70.109]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8cca4705c62sm92459226d6.27.2026.05.27.14.01.13 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 May 2026 14:01:14 -0700 (PDT) Date: Wed, 27 May 2026 17:01:12 -0400 From: Zach Miller To: Tanmay Kathpalia Cc: linux-mmc@vger.kernel.org, ulf.hansson@linaro.org, Adrian Hunter , linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 9/9] mmc: sdhci-cadence: add Altera Agilex5 SD6HC support Message-ID: <20260527210112.GB27846@criticallink.com> References: <20260511202132.5597-1-tanmay.kathpalia@altera.com> <20260511202132.5597-10-tanmay.kathpalia@altera.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260511202132.5597-10-tanmay.kathpalia@altera.com> On Mon, May 11, 2026 at 01:21:31PM -0700, Tanmay Kathpalia wrote: > +static const struct sdhci_ops sdhci_cdns6_agilex5_ops = { > + .set_clock = sdhci_set_clock, > + .get_timeout_clock = sdhci_cdns_get_timeout_clock, > + .set_bus_width = sdhci_set_bus_width, > + .reset = sdhci_reset, > + .platform_execute_tuning = sdhci_cdns_execute_tuning, > + .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, > + .hw_reset = sdhci_cdns6_hw_reset, > + .set_dma_mask = sdhci_cdns_set_dma_mask, > +}; > + > static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = { > .pltfm_data = { > .ops = &sdhci_cdns4_ops, > @@ -506,6 +544,16 @@ static const struct sdhci_cdns_drv_data sdhci_cdns4_drv_data = { > }, > }; > > +static const struct sdhci_cdns_drv_data sdhci_cdns6_agilex5_drv_data = { > + .pltfm_data = { > + .ops = &sdhci_cdns6_agilex5_ops, > + .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, > + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | > + SDHCI_QUIRK2_ACMD23_BROKEN, > + }, > + .dma_mask = DMA_BIT_MASK(40), > +}; Would it make sense to add SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN and set sdhci_pltfm_clk_get_max_clock() as the get_max_clock() op? The clock rate that function returns is already the one being overridden via sdhci-caps in device tree in patches 3 and 5. Since the infrastructure is there, it seems nicer to have this managed by the driver rather than requiring users to do it in device tree, especially because the clock rate is user-selectable via their FPGA design (so it's also a bit different from other caps which may need to be overridden). Best regards, Zach