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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-304ed2c3121sm179812eec.5.2026.05.28.18.05.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 18:05:42 -0700 (PDT) From: Fenglin Wu Subject: [PATCH v2 0/4] pinctrl: qcom: spmi-gpio: Add bidirectional level-shifter function support Date: Thu, 28 May 2026 18:05:34 -0700 Message-Id: <20260528-pinctrl-level-shifter-v2-0-3a6a025392bf@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIAF7mGGoC/4WNQQ6CMBREr0K6tqStUsCV9zAsoHzkG6DYXxoN4 e4WPICbSV4yM29lBA6B2DVZmYOAhHaKoE4JM309PYBjG5kpobTIVM5nnIx3Ax8gwMCpx86D46U qG1XoLivOLYvb2UGH7+P3Xv2YluYJxu9ne6NH8tZ9DnGQe++fI0guuCx1dtGyFXVubpYofS31Y Ow4pjFYtW3bF4AxUFzTAAAA X-Change-ID: 20260527-pinctrl-level-shifter-929b286f583d To: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski Cc: David Collins , Subbaraman Narayanamurthy , Kamal Wadhwa , Maulik Shah , kernel@oss.qualcomm.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Fenglin Wu X-Mailer: b4 0.16-dev-17187 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780016741; l=6363; i=fenglin.wu@oss.qualcomm.com; s=20260324; h=from:subject:message-id; bh=3ESj/5SnvDlYmVUSeBbRulZwu/xrSL5Nfdz9nul+puM=; b=hELj2pyvmwu7ZYnq9s5o4XDh0mJ+XOsdYKUqpdr8dZcCWDxgm2H/lPsTHQhqk0o5y7pwmyXKF amcXdxFQFp6DTfCWmfx3GUqT7lPmtNhTqqnoL/bXX0JcUOjHKR1QiEd X-Developer-Key: i=fenglin.wu@oss.qualcomm.com; a=ed25519; pk=hJdt3E7o54lql+miD2GaxwF74cDyhgNwMbmFOZ46bRU= X-Proofpoint-GUID: GTuzm3-Y2QyiGHp4VAlX60YnNgndcvR7 X-Proofpoint-ORIG-GUID: GTuzm3-Y2QyiGHp4VAlX60YnNgndcvR7 X-Authority-Analysis: v=2.4 cv=auOCzyZV c=1 sm=1 tr=0 ts=6a18e668 cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=bC-a23v3AAAA:8 a=EUspDBNiAAAA:8 a=jnkyZqLWQS9AGQwLeBEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=O8hF6Hzn-FEA:10 a=vr4QvYf-bLy2KjpDp97w:22 a=FO4_E8m0qiDe52t0p3_H:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI5MDAwNyBTYWx0ZWRfX/MTsb+zSpv6t dKxWBLAEli/5Os+jWyB+vnRHtxb10/sR3H4n6CSpejeG05LBchFXpTYfhjPeozIv/b7C5/T5A7y 442S6MFEi/F6wFvOaY2S3jMnohjBy/Wc9MZ+z9BgTVgGaokOQ0ElXsrMrj1/hgiVIZls5xWkC91 SFt2c2HcYrGV/9kWRQsgux2AgJMvgTOaUMl/fBCAmBFoN6CKQyD+N8TCWVtjJAq82Tl5oS7vzj3 HmKxa8A/H06diCYFxtDhZloDrc23v05sb2GTSOrr86L9FJFN6iADuTYSRcxDOfOLtfX6eUOGCNw R01pmRRoFHmr7IDcjG2f9X3DTBrVzMd4XyKANT0j6hUw4/Rs3sAJkPNmkeSR8CZ5dAQMzyEqI7X gScTc70rKdRBE1Y2qooI8u26SbiCJ0Hp4sIbZBgBVKyJoT4is1ostG5gMwXEC60Hvy964QaqpVD Br7YsU0uXDzSAYNjDQw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-28_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 impostorscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605290007 The PMH0101 PMIC introduces BIDIR_LVL_SHIFTER modules that provide bidirectional voltage translation between 1.2 V and 1.8 V power domains, targeting open-drain signal buses such as I2C. Each level shifter shares its two physical pins with a corresponding pair of GPIO modules, and its enable state is centrally managed by AOP firmware as a shared RPMh "XOB" resource. This series adds kernel support for controlling these level shifters through the pinctrl subsystem. Patches are ordered from infrastructure to driver to bindings: Patch 1 (soc: qcom: rpmh) extends the RPMh driver to accept write commands from devices that are not children of the RPMh controller. The existing write path assumes the caller is a child of the RSC device; however, the SPMI GPIO driver sits under the SPMI controller bus. Two new APIs are introduced — rpmh_get_ctrlr_dev() for resolving the controller from a "qcom,rpmh" DT phandle, and rpmh_write_ctrlr() / rpmh_write_async_ctrlr() which accept the controller device pointer directly rather than deriving it through the device parent chain. Patch 2 (dt-bindings) documents the new "level-shifter" function, the qcom,1p2v-1p8v-ls-en property, the qcom,rpmh phandle, and the qcom,pmic-id string required on pmh0101 nodes. The pmh0101 conditional block is split out from pmih0108 and given its own required properties. Patch 3 (pinctrl: qcom: spmi-gpio, rearchitect) refactors the driver's group and function registration to use the generic pinctrl group and function APIs (pinctrl_generic_add_group, pinmux_generic_add_function). The previous design treated every pin as its own group with access to all functions. The new design allows multi-pin groups with restricted function sets, which is a prerequisite for exposing the level-shifter function that is tied to specific GPIO pairs only. Patch 4 (pinctrl: qcom: spmi-gpio, level-shifter) builds on the above to introduce the "level-shifter" function. When selected, both GPIO pads in the pair are disabled (high-impedance), and the RPMh XOB vote for the level shifter is controlled separately via the new qcom,1p2v-1p8v-ls-en pinconf parameter, allowing enable and disable to be represented as distinct pinctrl states with the same function and group. With all these changes, the BIDIR_LVL_SHIFTER in PMH0101 could be controlled with following settings: &pmh0101_gpios { qcom,rpmh = <&apps_rsc>; qcom,pmic-id = "B_E0"; pmh0101-ls1-en { groups = "gpio11, gpio12"; function = "level-shifter"; qcom,1p2v-1p8v-ls-en = <1>; }; pmh0101-ls1-dis { groups = "gpio11, gpio12"; function = "level-shifter"; qcom,1p2v-1p8v-ls-en = <0>; }; }; Signed-off-by: Fenglin Wu --- Changes in v2: Add following change to address review comments from Sashiko AI: - PATCH 1, in drivers/soc/qcom/rpmh.c 1. Add rpmh_put_device() wrapper to avoid casting put_device directly to void (*)(void *) in devm_add_action_or_reset(), which would trigger a CFI kernel panic on indirect call type mismatch. 2. Add device_link_add() with DL_FLAG_AUTOREMOVE_CONSUMER | DL_FLAG_PM_RUNTIME in rpmh_get_ctrlr_dev() to enforce probe/remove ordering and runtime PM suspend/resume ordering between the RPMH controller and non-child consumer devices, preventing use-after-free and hardware state machine violations on unbind. - PATCH 2, in Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml 1. Make qcom,rpmh and qcom,pmic-id optional for qcom,pmh0101-gpio by removing them from the required list in the if/then conditional block. Update property descriptions to clarify they are only needed when the level-shifter function is used. - PATCH 3, in drivers/pinctrl/qcom/Kconfig 1. Add select GENERIC_PINCTRL_GROUPS and select GENERIC_PINMUX_FUNCTIONS to PINCTRL_QCOM_SPMI_PMIC to declare explicit dependencies on the generic pinctrl APIs (pinctrl_generic_add_group(), pinmux_generic_add_function(), etc.) used by the driver. - PATCH 3, in drivers/pinctrl/qcom/pinctrl-spmi-gpio.c 1. Switch from devm_pinctrl_register() to devm_pinctrl_register_and_init() + pinctrl_enable() to defer hog application until after all pin groups, functions, are fully registered, fixing a probe sequence bug where hogs would be applied against an incomplete pinctrl state. - PATCH 4, in drivers/pinctrl/qcom/pinctrl-spmi-gpio.c 1. Guard pad->is_enabled = true in pmic_gpio_pinconf_pin_set() to skip the assignment when pad->function == PMIC_GPIO_FUNC_INDEX_LEVEL_SHIFTER, preventing pinconf application from re-enabling GPIO pads that were explicitly disabled by the level-shifter mux path. 2. Call cmd_db_ready() before cmd_db_read_addr() in pmic_gpio_register_level_shifters() to propagate -EPROBE_DEFER when the command DB is not yet initialized, instead of incorrectly returning -ENODEV which causes a permanent probe failure. 3. Add qcom,rpmh / qcom,pmic-id DT property check before calling pmic_gpio_register_level_shifters() add make the level shifter function registration optional to match with the DT binding change. - Link to v1: https://patch.msgid.link/20260527-pinctrl-level-shifter-v1-0-1965461d0a7c@oss.qualcomm.com --- Fenglin Wu (4): soc: qcom: rpmh: Allow non-child devices to issue write commands dt-bindings: pinctrl: qcom,pmic-gpio: Add level-shifter function pinctrl: qcom: spmi-gpio: Rearchitect for flexible group support pinctrl: qcom: spmi-gpio: Add level-shifter function support .../bindings/pinctrl/qcom,pmic-gpio.yaml | 66 +- drivers/pinctrl/qcom/Kconfig | 2 + drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 796 ++++++++++++++++----- drivers/soc/qcom/rpmh.c | 173 ++++- include/dt-bindings/pinctrl/qcom,pmic-gpio.h | 1 + include/soc/qcom/rpmh.h | 21 + 6 files changed, 845 insertions(+), 214 deletions(-) --- base-commit: b8f192cec7dcb2e4f04ee57ab78d51777b0a5729 change-id: 20260527-pinctrl-level-shifter-929b286f583d Best regards, -- Fenglin Wu