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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SN1PEPF00036F43.mail.protection.outlook.com (10.167.248.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.71.7 via Frontend Transport; Thu, 28 May 2026 05:19:33 +0000 Received: from purico-ed03host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Thu, 28 May 2026 00:19:29 -0500 From: Suravee Suthikulpanit To: , , , CC: , , , , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 19/26] iommu/amd: Add per-segment translate device ID pool Date: Thu, 28 May 2026 05:17:31 +0000 Message-ID: <20260528051738.596013-20-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260528051738.596013-1-suravee.suthikulpanit@amd.com> References: <20260528051738.596013-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F43:EE_|IA1PR12MB6041:EE_ X-MS-Office365-Filtering-Correlation-Id: a997875f-3192-41b5-18fd-08debc78b44f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|1800799024|36860700016|18002099003|22082099003|3023799007|11063799006|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1Rdl693ZP3kIWuWWWRdsXwc8bC0Vb89hUM4oFrbImcdL6MxNDz6/2/+ZXvicpedkM31hYwTaPz+9JvNwVULLkuuLayhV4rioHh7lHDIiCkcBeEoYiBv1Pf3xaKoiera/wvvADCQWBh86C92r0ky1+nnP2vp6SyOJ72FbeXavTgR0DsKooWEqYDNtFHp373Usd/pXQSBOjzppm75FCwG878Be2x92q7SsymNl8TFkae611NlInwPPGzHQqkeR8vjMmGJzGlPGz6cf5lz4n2AWSV5Pmv9b/MnLxhlRa9w+1BAVkSSgtd0EfsERWv1r3B3q1sFtNzD6h5QjeMZCkYvSPUoX4HTszQEiejo3zjv8TniLxDPE0kCumWyLtxv8dB4k4HIE3jNB2v0oc22JJJ+sZBC1S3VyMhducmUkKIB1lf2pWGEfwkgrjR5DFIhq6/LB X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2026 05:19:33.9714 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a997875f-3192-41b5-18fd-08debc78b44f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F43.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6041 Track translate-device-id slots per PCI segment so real PCI device IDs can be reserved for normal DTE programming and excluded from dynamic allocation for vIOMMU translation DTEs. Add amd_iommu_pci_seg_trans_devid_init/fini() during segment setup and teardown, amd_iommu_trans_devid_reserve() for attach-time reservation, and trans_devid.c implementing the xarray-backed state machine. Call the reserve hook from amd_iommu_attach_device() before programming the DTE. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/Makefile | 2 +- drivers/iommu/amd/amd_iommu.h | 12 +++++ drivers/iommu/amd/amd_iommu_types.h | 17 ++++++ drivers/iommu/amd/init.c | 3 ++ drivers/iommu/amd/iommu.c | 12 +++++ drivers/iommu/amd/trans_devid.c | 80 +++++++++++++++++++++++++++++ 6 files changed, 125 insertions(+), 1 deletion(-) create mode 100644 drivers/iommu/amd/trans_devid.c diff --git a/drivers/iommu/amd/Makefile b/drivers/iommu/amd/Makefile index e1e824b9c7b0..12c3fe83e4ce 100644 --- a/drivers/iommu/amd/Makefile +++ b/drivers/iommu/amd/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y += iommu.o init.o quirks.o ppr.o pasid.o -obj-$(CONFIG_AMD_IOMMU_IOMMUFD) += iommufd.o nested.o viommu.o +obj-$(CONFIG_AMD_IOMMU_IOMMUFD) += iommufd.o nested.o viommu.o trans_devid.o obj-$(CONFIG_AMD_IOMMU_DEBUGFS) += debugfs.o diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index d1640181b292..d411bc326241 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -216,6 +216,18 @@ void amd_iommu_update_dte(struct amd_iommu *iommu, struct dev_table_entry *new); int amd_iommu_completion_wait(struct amd_iommu *iommu); +/* Per-segment translate-device-id pool (CONFIG_AMD_IOMMU_IOMMUFD) */ +#ifdef CONFIG_AMD_IOMMU_IOMMUFD +void amd_iommu_pci_seg_trans_devid_init(struct amd_iommu_pci_seg *pci_seg); +void amd_iommu_pci_seg_trans_devid_fini(struct amd_iommu_pci_seg *pci_seg); +int amd_iommu_trans_devid_reserve(struct amd_iommu_pci_seg *pci_seg, u16 id); +#else +static inline void +amd_iommu_pci_seg_trans_devid_init(struct amd_iommu_pci_seg *pci_seg) { } +static inline void +amd_iommu_pci_seg_trans_devid_fini(struct amd_iommu_pci_seg *pci_seg) { } +#endif + void amd_iommu_set_translate_dte(struct amd_iommu *iommu, u16 gid, struct protection_domain *pdom, u32 devid); diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 2d7bc791dbd9..ffa338c8735f 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -615,6 +615,14 @@ PT_IOMMU_CHECK_DOMAIN(struct protection_domain, iommu, domain); PT_IOMMU_CHECK_DOMAIN(struct protection_domain, amdv1.iommu, domain); PT_IOMMU_CHECK_DOMAIN(struct protection_domain, amdv2.iommu, domain); +#ifdef CONFIG_AMD_IOMMU_IOMMUFD +enum trans_devid_state { + TRANS_DEVID_FREE = 0, + TRANS_DEVID_RESERVED, + TRANS_DEVID_ALLOCATED, +}; +#endif + /* * This structure contains information about one PCI segment in the system. */ @@ -676,6 +684,15 @@ struct amd_iommu_pci_seg { * parsing time. */ struct list_head unity_map; + +#ifdef CONFIG_AMD_IOMMU_IOMMUFD + /* + * Per-segment translate-device-id allocation. The xarray is indexed by + * the translate-device-id. The value is the state (enum trans_devid_state). + */ + struct mutex trans_devid_mutex; + struct xarray trans_devid_xa; +#endif }; /* diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 6e69b3dd8b1e..622bc0337eda 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -1737,6 +1737,8 @@ static struct amd_iommu_pci_seg *__init alloc_pci_segment(u16 id, if (alloc_rlookup_table(pci_seg)) goto err_free_alias_table; + amd_iommu_pci_seg_trans_devid_init(pci_seg); + return pci_seg; err_free_alias_table: @@ -1768,6 +1770,7 @@ static void __init free_pci_segments(void) for_each_pci_segment_safe(pci_seg, next) { list_del(&pci_seg->list); + amd_iommu_pci_seg_trans_devid_fini(pci_seg); free_irq_lookup_table(pci_seg); free_rlookup_table(pci_seg); free_alias_table(pci_seg); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 6c4c4f62ddde..2600af84c8ca 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3055,6 +3055,18 @@ static int amd_iommu_attach_device(struct iommu_domain *dom, struct device *dev, if (dom->dirty_ops && !amd_iommu_hd_support(iommu)) return -EINVAL; +#if IS_ENABLED(CONFIG_AMD_IOMMU_IOMMUFD) + /* Translate-device-id reservation must be done before setting up + * the DTE for the device to make sure that the id has not been allocated + * yet. (See amd_iommu_trans_devid_alloc().) + */ + ret = amd_iommu_trans_devid_reserve(iommu->pci_seg, dev_data->devid); + if (ret) { + pr_err("%s: Failed to reserve device id %#x\n", __func__, dev_data->devid); + return ret; + } +#endif + if (dev_data->domain) detach_device(dev); diff --git a/drivers/iommu/amd/trans_devid.c b/drivers/iommu/amd/trans_devid.c new file mode 100644 index 000000000000..f15cbaae9118 --- /dev/null +++ b/drivers/iommu/amd/trans_devid.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + * + * AMD vIOMMU translate-device-id pool per PCI segment. + */ + +#include +#include + +#include "amd_iommu.h" + +static inline enum trans_devid_state trans_devid_xa_get_state(void *entry) +{ + if (!entry) + return TRANS_DEVID_FREE; + if (WARN_ON_ONCE(!xa_is_value(entry))) + return TRANS_DEVID_FREE; + return (enum trans_devid_state)xa_to_value(entry); +} + +static inline void *trans_devid_xa_mk_state(enum trans_devid_state s) +{ + return xa_mk_value((unsigned long)s); +} + +void amd_iommu_pci_seg_trans_devid_init(struct amd_iommu_pci_seg *pci_seg) +{ + mutex_init(&pci_seg->trans_devid_mutex); + xa_init(&pci_seg->trans_devid_xa); +} + +void amd_iommu_pci_seg_trans_devid_fini(struct amd_iommu_pci_seg *pci_seg) +{ + xa_destroy(&pci_seg->trans_devid_xa); +} + +/** + * amd_iommu_trans_devid_reserve - occupy @id so it is never returned by alloc + * + * Reservation is done when attaching device to a domain (see amd_iommu_attach_device()). + * + * Note: Since PCI hot-plug devices are enumerated during runtime, they could clash + * with the translate-device-id allocation. In such case, amd_iommu_trans_devid_reserve() + * could fail with %-EBUSY. This can be avoided by reserving the hot-plug id range if it + * is known in advance. + * + * Return: 0 on success, %-EBUSY if @id is already allocated. A second reserve of + * an already-reserved @id succeeds. + */ +int amd_iommu_trans_devid_reserve(struct amd_iommu_pci_seg *pci_seg, u16 id) +{ + void *entry, *old; + int ret = 0; + + mutex_lock(&pci_seg->trans_devid_mutex); + entry = xa_load(&pci_seg->trans_devid_xa, id); + switch (trans_devid_xa_get_state(entry)) { + case TRANS_DEVID_ALLOCATED: + ret = -EBUSY; + break; + case TRANS_DEVID_RESERVED: + break; + case TRANS_DEVID_FREE: + old = xa_store(&pci_seg->trans_devid_xa, id, + trans_devid_xa_mk_state(TRANS_DEVID_RESERVED), GFP_KERNEL); + if (xa_is_err(old)) { + ret = xa_err(old); + break; + } + WARN_ON_ONCE(old); + break; + } + mutex_unlock(&pci_seg->trans_devid_mutex); + + if (!ret) + pr_debug("%s: Reserved trans_devid %#x (seg %#x)\n", __func__, id, + pci_seg->id); + return ret; +} -- 2.34.1