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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CH3PEPF00000009.mail.protection.outlook.com (10.167.244.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.71.7 via Frontend Transport; Thu, 28 May 2026 05:19:39 +0000 Received: from purico-ed03host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Thu, 28 May 2026 00:19:33 -0500 From: Suravee Suthikulpanit To: , , , CC: , , , , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 20/26] iommu/amd: Reserve translate-device-id for PCI requestor aliases Date: Thu, 28 May 2026 05:17:32 +0000 Message-ID: <20260528051738.596013-21-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260528051738.596013-1-suravee.suthikulpanit@amd.com> References: <20260528051738.596013-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000009:EE_|LV8PR12MB9666:EE_ X-MS-Office365-Filtering-Correlation-Id: 25851409-32b0-42a6-6c70-08debc78b753 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|7416014|376014|1800799024|82310400026|22082099003|18002099003|11063799006|56012099006|5023799004|6133799003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: rRKb6DznDWe4jTBzSyhHXJbBu6dsUC7FXYJSpw2lsmTSxF+quM7RUrG97IrnzAuW/giG0MxzHxM8vjLubOkljwNH6cLy5zrngrRCzbi0PJk7uaRwaaE/JqKB+N8/3zrM0jvWcjjCB0qNm967R1WgYZ0Vb1jiIjRX+9ZY84yK3aQOyqrYir+cc4NR4efTwAtaCUWNrlwKBFsUa5amUZzYuTONd30Tts4IE/H+tP2eByP+Cuzl3XR+/z1gf7A9SWC4GJxE4ArNFjtzCH57HKqKGBOiyN+4Y9teDhAYBmWNIY1qKd1H/sc+SCvLRNG8Tce5rfYlOP0VHewcW4lFbeT/4j+tdabdD/IfDiip0U7YThU0DqI0xrrd5vJpk1XGiVIJSsJ56W53krAyq8Iom03kogggb6yzFLiI1WmtxdhGz8G4WC+US3yhjkH7IoT5TdDI X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2026 05:19:39.0667 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 25851409-32b0-42a6-6c70-08debc78b753 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000009.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9666 The per-segment translate-device-id (trans_devid) pool hands out numeric device-table indices used by the AMD vIOMMU / iommufd path (e.g. mapping a KVM file descriptor to a shared trans_devid). amd_iommu_attach_device() already calls amd_iommu_trans_devid_reserve() for the struct device's own PCI BDF so that id cannot later be returned by the allocator. That is not sufficient on its own. The AMD IOMMU driver programs identical DMA translation device-table entries (DTEs) for every requestor ID that can issue DMA on behalf of the same PCI function: the IVRS alias from alias_table[] when it is not covered by the PCI DMA-alias walk (different bus than the device), and every alias visited by pci_for_each_dma_alias(). Those alternate BDFs are not separate struct device attach targets, so they never received a trans_devid reservation and could in principle collide with a dynamically allocated trans_devid. Introduce amd_iommu_trans_devid_reserve_pci_aliases() in trans_devid.c and invoke it from amd_iommu_attach_device() immediately after the primary amd_iommu_trans_devid_reserve() succeeds. For PCI devices the helper reserves the IVRS alias when it differs from the device BDF, then walks pci_for_each_dma_alias() and reserves each alias BDF. Repeated attach and overlap with the primary BDF in the PCI walk are handled by the existing idempotency of amd_iommu_trans_devid_reserve() (a second reserve of an already-reserved id succeeds). Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 2 ++ drivers/iommu/amd/iommu.c | 7 +++++ drivers/iommu/amd/trans_devid.c | 45 +++++++++++++++++++++++++++++++++ 3 files changed, 54 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index d411bc326241..ddfc6329d235 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -221,6 +221,8 @@ int amd_iommu_completion_wait(struct amd_iommu *iommu); void amd_iommu_pci_seg_trans_devid_init(struct amd_iommu_pci_seg *pci_seg); void amd_iommu_pci_seg_trans_devid_fini(struct amd_iommu_pci_seg *pci_seg); int amd_iommu_trans_devid_reserve(struct amd_iommu_pci_seg *pci_seg, u16 id); +int amd_iommu_trans_devid_reserve_pci_aliases(struct amd_iommu *iommu, + struct device *dev); #else static inline void amd_iommu_pci_seg_trans_devid_init(struct amd_iommu_pci_seg *pci_seg) { } diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 2600af84c8ca..2f9ca8f2d3c6 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3065,6 +3065,13 @@ static int amd_iommu_attach_device(struct iommu_domain *dom, struct device *dev, pr_err("%s: Failed to reserve device id %#x\n", __func__, dev_data->devid); return ret; } + + ret = amd_iommu_trans_devid_reserve_pci_aliases(iommu, dev); + if (ret) { + pr_err("%s: Failed to reserve translate devid for alias of %#x (err %d)\n", + __func__, dev_data->devid, ret); + return ret; + } #endif if (dev_data->domain) diff --git a/drivers/iommu/amd/trans_devid.c b/drivers/iommu/amd/trans_devid.c index f15cbaae9118..76450d1735e2 100644 --- a/drivers/iommu/amd/trans_devid.c +++ b/drivers/iommu/amd/trans_devid.c @@ -6,6 +6,7 @@ */ #include +#include #include #include "amd_iommu.h" @@ -78,3 +79,47 @@ int amd_iommu_trans_devid_reserve(struct amd_iommu_pci_seg *pci_seg, u16 id) pci_seg->id); return ret; } + +static int reserve_trans_devid_each_dma_alias(struct pci_dev *pdev, u16 alias, + void *data) +{ + struct amd_iommu_pci_seg *pci_seg = data; + + (void)pdev; + return amd_iommu_trans_devid_reserve(pci_seg, alias); +} + +/** + * amd_iommu_trans_devid_reserve_pci_aliases - reserve translate-device-ids for + * PCI DMA aliases and for the IVRS alias when it is not walked as a PCI DMA + * alias (different bus). Idempotent for repeated attach; see + * amd_iommu_trans_devid_reserve(). + * + * Return: 0 on success or if @dev is not PCI; otherwise an errno from + * amd_iommu_trans_devid_reserve() or pci_for_each_dma_alias(). + */ +int amd_iommu_trans_devid_reserve_pci_aliases(struct amd_iommu *iommu, + struct device *dev) +{ + struct pci_dev *pdev; + struct amd_iommu_pci_seg *pci_seg; + u16 devid, ivrs_alias; + int ret; + + if (!dev_is_pci(dev)) + return 0; + + pdev = to_pci_dev(dev); + pci_seg = iommu->pci_seg; + devid = pci_dev_id(pdev); + + ivrs_alias = pci_seg->alias_table[devid]; + if (ivrs_alias != devid) { + ret = amd_iommu_trans_devid_reserve(pci_seg, ivrs_alias); + if (ret) + return ret; + } + + return pci_for_each_dma_alias(pdev, reserve_trans_devid_each_dma_alias, + pci_seg); +} -- 2.34.1