From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D6BA3403E7 for ; Thu, 28 May 2026 19:00:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.50 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779994849; cv=none; b=EpstX08FLPgwLk+aNV6imGeGp2UJnBWvRGMJgTRSPhPFWoE3XeWoiWmm4SMyN0Vep1UMiJEbjX+/wvkv9iSFtWe8ikRhURkwlFhfK78Vs8oAuW91MTEwShPmN32UBG6UQX3B/ZAv7rivK/RwbeMsKOavmEg1fpgrTOgPqjjdQ+4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779994849; c=relaxed/simple; bh=G3QQpR8rFP9MtjIXSfetY6TLu8NVajep3IQklei1i4s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d5VoojOOR6BCSwUdl5PK2Vr6g9/AJ1DAbci5LvvlifTEuymPPnSvYo/5ktvV/6vgOgUUSqHei5QSh25JKHfuIHN85o5Zh1iCDLteG+3YdcxE0RZdta35/RBTmLdI2AWep0heyAlGkfALZzcGfV0+tAm7aEtYgIBIzF3AXe8Zmc4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=OstW3Qcr; arc=none smtp.client-ip=209.85.221.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OstW3Qcr" Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-44e1860558fso8261989f8f.0 for ; Thu, 28 May 2026 12:00:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779994820; x=1780599620; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HMXXtYGcE9eK212AumCdNI+6/leOGhk7hdPMWy8VAbo=; b=OstW3QcrQtCVFZc2uaEns05VF3FuZ8UMYncjTgWVKxrgQbIawGITqdihbhBySIVBG8 GmP3uVljiEoaaDBXKcrnAiBUS+ePi/ec9gBVASI/NlcTUCN6wBcQlDgssNKCgqBoQq5Z L82ErrR1960QihtI8GvTkKzML5joVBtTsJ+SVciOfCNB5ZF84DF07LeQJBYLuZMFpSuW Orow+l5fJbNeS46EPL0t+pgIUZFpXiyTWHpG+pOZmGQ3drzST02V5iV4N850MQLKEqPP D9eK+RWsWovSMjbIFGby5U12MFXGgTdTkPQ44a9ZkCgVHq3oNh6pTGoolbGCYq1Iq+b6 z9ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779994820; x=1780599620; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=HMXXtYGcE9eK212AumCdNI+6/leOGhk7hdPMWy8VAbo=; b=eOWoKNX4o0txSlLBs1iykrzxvrskeovbmLHLG3j7XKkegPNaZvFHz/IS9MCMrxgIXT hkO2E9fVtDWfhfJ2lAQktGJ7ecSRgU3/YfgQO+QHR5ELXtnmx1GAY589jZM83kWpBS2g FoWL38Luu9RYhmvGEP6EQqaASwp7D2nZJ1yfDtUdmY/LZX/Q0D46P2vKvmjfVMJAclDo 8pQ4BrI6ORz8E9GF3IQuxXBldarCqavA9EmXraL6VKkIuNGwy6fPFBZgyy+XTGKmea6l r2em7VXEHRXorEXDk0XttM9zBPHPeNQzpVaHPLEjNYoIVQx0B3yTmwUDzlXY1Ie2/SVv lLJA== X-Forwarded-Encrypted: i=1; AFNElJ/VNXGihQedFF5vM8wOBRiw6rw1UCVtRQoYZpoJ22ZPclmnmNegbfLG+/ZmgL3byuhcie6V/GkjAUakNvY=@vger.kernel.org X-Gm-Message-State: AOJu0YwHp6Qg+0N0ABccvZaEiDruxfig3PFRy2XsNMi7VChCISPTfjiX nTeO5O6BSOvKNvk4dKeh0tOCjNfpQl7TgLFx+8tQUecWxbcMim7JgC8dbv7QqA== X-Gm-Gg: Acq92OF4BpvNbu6XjF4xJ2yycYav17Ro8T+5omknMSQkK216q2ttPwhgOhNgV7G6cIh AdVAPPCtlk4uIQurDr10zGimyRqk5NlnR4E8Nem2N6d5at8FZ8HDLNuP8E8bdIfsFd0EZEvlIY6 9mSy4T3mGelhxr6hHEusutoH9G85DM2QX9+Q/USohHPAgJodpgpZ+2/dsVmNkLa2wbN5CvJVyyY HcOp+IZijoooOc8sUz8HSmtbG/L55YXvzh8umOxTXCfJkU/XWDOJmZj8irY9rKN8U4RxVB9cCuS iQEDd05RhEaQ/dHh8ewU/PuTcDPsbBiXG+YbAab5JiZGsWeyKFHUGxIj2fO8Iyc1p6JaQrjNkEZ 6UmvON5O/K21TNfNfgUZJK4THHl1yraf2VIE7GnF3EzRYmtkOJWOw8S0vO1rVkqkYvIHK4wdOl4 10/8Lc491sdKmYmY0T57B5Is7IVsPdUwITbB/48ss1epFW7JJvVTgtTzlntScWIqWq2BI0OALTb cEHrKU= X-Received: by 2002:a05:6000:1006:b0:45d:817c:b8b2 with SMTP id ffacd0b85a97d-45ef05f84f1mr517631f8f.30.1779994820053; Thu, 28 May 2026 12:00:20 -0700 (PDT) Received: from Ansuel-XPS24 (host-79-42-252-49.retail.telecomitalia.it. [79.42.252.49]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-45ee2a12a69sm8625408f8f.16.2026.05.28.12.00.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 12:00:18 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v5 2/3] clk: en7523: generalize register clocks function Date: Thu, 28 May 2026 20:59:55 +0200 Message-ID: <20260528190000.9164-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260528190000.9164-1-ansuelsmth@gmail.com> References: <20260528190000.9164-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Airoha AN7583 SoC will use the same logic used by Airoha EN7581 SoC to register clocks. Generalize it to register clocks defined in soc_data. Add the clocks definition in EN7581 SoC to support this new implementation. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 1ab0e2eca5d3..087ff4568124 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -115,6 +115,7 @@ struct en_rst_data { struct en_clk_soc_data { u32 num_clocks; + const struct en_clk_desc *base_clks; const struct clk_ops pcie_ops; int (*hw_init)(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data); @@ -711,12 +712,15 @@ static int en7523_clk_hw_init(struct platform_device *pdev, static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, struct regmap *map, void __iomem *base) { + const struct en_clk_soc_data *soc_data; struct clk_hw *hw; u32 rate; int i; - for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) { - const struct en_clk_desc *desc = &en7581_base_clks[i]; + soc_data = device_get_match_data(dev); + + for (i = 0; i < soc_data->num_clocks - 1; i++) { + const struct en_clk_desc *desc = &soc_data->base_clks[i]; u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg; int err; @@ -991,6 +995,7 @@ static const struct en_clk_soc_data en7523_data = { }; static const struct en_clk_soc_data en7581_data = { + .base_clks = en7581_base_clks, /* We increment num_clocks by 1 to account for additional PCIe clock */ .num_clocks = ARRAY_SIZE(en7581_base_clks) + 1, .pcie_ops = { -- 2.53.0