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Thu, 28 May 2026 14:55:15 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Date: Fri, 29 May 2026 00:53:02 +0300 Subject: [PATCH RFC v3 5/5] ARM: dts: zte: Declare a zx297520v3 clock device nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20260529-zx29clk-v3-5-c7fe54ea388f@gmail.com> References: <20260529-zx29clk-v3-0-c7fe54ea388f@gmail.com> In-Reply-To: <20260529-zx29clk-v3-0-c7fe54ea388f@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Brian Masney Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Stefan_D=C3=B6singer?= X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3665; i=stefandoesinger@gmail.com; h=from:subject:message-id; bh=eKCYysFcPuaXaoisFpLloAByZzjH3S4RlmU0j/f/7Ww=; b=owEBiQJ2/ZANAwAIAT0TvMhUTxoiAcsmYgBqGLmonB1gQW4rZ70oU0qgrlZbtOo5IBUL5cz8K uiR7j+xheuJAk8EAAEIADkWIQRDFvS2qgVbJ5UyXWw9E7zIVE8aIgUCahi5qBsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMiwyLDIACgkQPRO8yFRPGiJ44Q/8CIR9L5lArAiX4KXK9TNo8gozsOA+QtY xAaPTNtdFAYbufZxCearH5SOwIkECPWNXkoOHUgsqUkovgW9ytiFBM69T8PQHAbwEMq7tVnYFt3 aE8SIFT7ExX5DKfG6TXFphrQcBkMoE1u8uv2d01pjRgs61xruYaGHsyIfjTbXn+4LIYpkGbZZcC p7O9mFhIkdna1PVWHx089Iq6jxx/2FOzfG0BdXVeTSNWwNhPE35VbGcTXxAIoFUECuoJZti/X6F zpr6kW8MY/kQ+ei71gaXAu2qrAPkg/W0NvV7owyKZAMYwGTbcDEUyxjW1yEqZSU5cGh5lpXJWjp uHJlsPCQ9DRQrmK/FcNaXRhE2GEMn7vZyKrKv57N1UogMS4ujjEBixkth6UjbC58nX4QNxM16Yj u/ctOLfzxCs5yjjvLMaTquro6kYv/Knh29PqekhtBEHq02JtZVFWUEohnBrzazD7WshWfm9Ng2q t5ToJPcsNzljawo7O9fBuuwqMhYqDOGhy1GZ+Ldq/f7Ft+/R4hb6hTqRREizKKl8+HhgjJQKOuJ pfYymxTsmB4iiTbEn4DVHLIq9DXnAQuL7Pztxvrfiq/du+2hgn2JGjSTj3G9pCbakLYCmV+qVCD Qnt1VogpwWWBkC2wl4JZzSECG3uiiam134qXk8hCLGtPbIBK3P2c= X-Developer-Key: i=stefandoesinger@gmail.com; a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 This makes use of the driver added in the previous patches. It wires up the uart clocks and resets and allows getting rid of the placeholder uartclk node. Signed-off-by: Stefan Dösinger --- arch/arm/boot/dts/zte/zx297520v3.dtsi | 55 ++++++++++++++++++++++++++++++----- 1 file changed, 47 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/zte/zx297520v3.dtsi b/arch/arm/boot/dts/zte/zx297520v3.dtsi index a16c30a164bb..9d80740ccf8a 100644 --- a/arch/arm/boot/dts/zte/zx297520v3.dtsi +++ b/arch/arm/boot/dts/zte/zx297520v3.dtsi @@ -4,6 +4,7 @@ */ #include +#include / { #address-cells = <1>; @@ -20,13 +21,16 @@ cpu@0 { }; }; - /* Base bus clock and default for the UART. It will be replaced once a clock driver has - * been added. - */ - uartclk: uartclk-26000000 { - #clock-cells = <0>; + osc26m: osc26m { compatible = "fixed-clock"; clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + osc32k: osc32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; timer { @@ -70,13 +74,46 @@ gic: interrupt-controller@f2000000 { <0xf2040000 0x20000>; }; + + topclk: clk@13b000 { + compatible = "zte,zx297520v3-topclk"; + reg = <0x0013b000 0x400>, + <0x01306000 0x400>; + reg-names = "top", "matrix"; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&osc26m>, <&osc32k>; + clock-names = "osc26m", "osc32k"; + }; + + lspclk: clk@1400000 { + compatible = "zte,zx297520v3-lspclk"; + reg = <0x01400000 0x100>; + #clock-cells = <1>; + #reset-cells = <1>; + + clocks = <&topclk ZX297520V3_LSP_MPLL_D5_WCLK>, + <&topclk ZX297520V3_LSP_MPLL_D4_WCLK>, + <&topclk ZX297520V3_LSP_MPLL_D6_WCLK>, + <&topclk ZX297520V3_LSP_MPLL_D8_WCLK>, + <&topclk ZX297520V3_LSP_MPLL_D12_WCLK>, + <&topclk ZX297520V3_LSP_OSC26M_WCLK>, + <&topclk ZX297520V3_LSP_OSC32K_WCLK>, + <&topclk ZX297520V3_LSP_PCLK>, + <&topclk ZX297520V3_LSP_TDM_WCLK>, + <&topclk ZX297520V3_LSP_DPLL_D4_WCLK>; + clock-names = "mpll_d5", "mpll_d4", "mpll_d6", "mpll_d8", "mpll_d12", + "osc26m", "osc32k", "pclk", "tdm_wclk", "dpll_d4"; + }; + uart0: serial@131000 { compatible = "arm,pl011", "arm,primecell"; arm,primecell-periphid = <0x0018c011>; reg = <0x00131000 0x1000>; interrupts = ; - clocks = <&uartclk>, <&uartclk>; + clocks = <&topclk ZX297520V3_UART0_WCLK>, <&topclk ZX297520V3_UART0_PCLK>; clock-names = "uartclk", "apb_pclk"; + resets = <&topclk ZX297520V3_UART0_RESET>; status = "disabled"; }; @@ -85,8 +122,9 @@ uart1: serial@1408000 { arm,primecell-periphid = <0x0018c011>; reg = <0x01408000 0x1000>; interrupts = ; - clocks = <&uartclk>, <&uartclk>; + clocks = <&lspclk ZX297520V3_UART1_WCLK>, <&lspclk ZX297520V3_UART1_PCLK>; clock-names = "uartclk", "apb_pclk"; + resets = <&lspclk ZX297520V3_UART1_RESET>; status = "disabled"; }; @@ -95,8 +133,9 @@ uart2: serial@140d000 { arm,primecell-periphid = <0x0018c011>; reg = <0x0140d000 0x1000>; interrupts = ; - clocks = <&uartclk>, <&uartclk>; + clocks = <&lspclk ZX297520V3_UART2_WCLK>, <&lspclk ZX297520V3_UART2_PCLK>; clock-names = "uartclk", "apb_pclk"; + resets = <&lspclk ZX297520V3_UART2_RESET>; status = "disabled"; }; }; -- 2.53.0