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Fri, 29 May 2026 15:56:09 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.87.85.9]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 29 May 2026 15:56:09 +0000 (GMT) From: Steffen Eiden To: kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org Cc: Alexander Gordeev , Andreas Grapentin , Arnd Bergmann , Catalin Marinas , Christian Borntraeger , Claudio Imbrenda , David Hildenbrand , Friedrich Welter , Gautam Gala , Hariharan Mari , Heiko Carstens , Hendrik Brueckner , Ilya Leoshkevich , Janosch Frank , Joey Gouly , Marc Zyngier , Nico Boehr , Nina Schoetterl-Glausch , Oliver Upton , Paolo Bonzini , Suzuki K Poulose , Sven Schnelle , Ulrich Weigand , Vasily Gorbik , Will Deacon , Zenghui Yu Subject: [PATCH v1 20/26] KVM: arm64: Share ID reg handling Date: Fri, 29 May 2026 17:55:53 +0200 Message-ID: <20260529155601.2927240-21-seiden@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260529155601.2927240-1-seiden@linux.ibm.com> References: <20260529155601.2927240-1-seiden@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=fIYJG5ae c=1 sm=1 tr=0 ts=6a19b722 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=VnNF1IyMAAAA:8 a=zX106nZOjTGFKEJQ2UEA:9 X-Proofpoint-ORIG-GUID: ZzHTE0AERXso7IIrM-FN81R4I5MxuTO1 X-Proofpoint-GUID: ZzHTE0AERXso7IIrM-FN81R4I5MxuTO1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI5MDE1NiBTYWx0ZWRfX2vj6YkRj7S/C /fxSSkbOGVA5zBBSZdvjrlGMcnXyGE4kTca+RTxJLMmJsXkDHQFXBNywofBFuGNuvi3ZISjzWco 1HUwkMl1+js7fUQItP6Kp7bfj9rm84EQgt4+imjAEFLqtMfPgRnDtFdqq7yHFvUzZVzqAdAtSN0 aaCiARNmGFqHoFqzaiZBVQ4O2DFXi0XBCKg4ffzO3IRJr1yz8sYlIjaYcdBJ6RBPj+QyeV8iVZ3 SuhMcQLOkESCjOntKD5rZfHaZ9Wru02+ElmA7bGNb1ff2fwoIQzJR5NFE2mC1WPLroKkU00BJZg sB3vf8JpvAi8ZopBrJW1QQ9QEURxjgAlUvkNESpoiXGBGrVHwCejNHCEaOAXQuW6HA/Fq2yEa2I lmwlAq3XYm6a3CGhR9ZWSZ+r4TdSyRtZp4Nk/wVNja0D8sQCXf44s4CuqtHpmgaZr6Z8j9e/gFh EiE/w34gfmchWc+mn7g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-29_04,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 adultscore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605290156 Move ID register definitions from arch/arm64/include to a shared location (include/kvm/arm64) to enable reuse by e.g. s390 for KVM/arm64 on s390 support. Signed-off-by: Steffen Eiden --- arch/arm64/include/asm/kvm_host.h | 41 ------------------------------ include/kvm/arm64/kvm_host.h | 42 +++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 41 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 5734e93cad57..a5fca468cc4a 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1385,47 +1385,6 @@ static inline void kvm_hyp_reserve(void) { } void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu); bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu); -struct kvm_vm_id_regs { - /* - * Emulated CPU ID registers per VM - * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it - * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. - * - * These emulated idregs are VM-wide, but accessed from the context of a vCPU. - * Atomic access to multiple idregs are guarded by kvm_arch.config_lock. - */ -#define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) -#define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1) - u64 normal[KVM_ARM_ID_REG_NUM]; - - u64 midr_el1; - u64 revidr_el1; - u64 aidr_el1; - u64 ctr_el0; -}; - -static inline u64 *__vm_id_reg(struct kvm_vm_id_regs *id_regs, u32 reg) -{ - switch (reg) { - case sys_reg(3, 0, 0, 1, 0) ... sys_reg(3, 0, 0, 7, 7): - return &id_regs->normal[IDREG_IDX(reg)]; - case SYS_CTR_EL0: - return &id_regs->ctr_el0; - case SYS_MIDR_EL1: - return &id_regs->midr_el1; - case SYS_REVIDR_EL1: - return &id_regs->revidr_el1; - case SYS_AIDR_EL1: - return &id_regs->aidr_el1; - default: - WARN_ON_ONCE(1); - return NULL; - } -} - -#define kvm_read_vm_id_reg(kvm, reg) \ - ({ u64 __val = *__vm_id_reg(&(kvm)->arch.id_regs, reg); __val; }) - void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val); static inline bool kvm_arch_has_irq_bypass(void) diff --git a/include/kvm/arm64/kvm_host.h b/include/kvm/arm64/kvm_host.h index 8bf399508757..379942225d5f 100644 --- a/include/kvm/arm64/kvm_host.h +++ b/include/kvm/arm64/kvm_host.h @@ -4,6 +4,7 @@ #define __KVM_ARM64_KVM_HOST_H #include +#include #define KVM_VCPU_MAX_FEATURES 9 @@ -21,6 +22,47 @@ #define KVM_REQ_MAP_L1_VNCR_EL2 KVM_ARCH_REQ(10) #define KVM_REQ_VGIC_PROCESS_UPDATE KVM_ARCH_REQ(11) +struct kvm_vm_id_regs { + /* + * Emulated CPU ID registers per VM + * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it + * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. + * + * These emulated idregs are VM-wide, but accessed from the context of a vCPU. + * Atomic access to multiple idregs are guarded by kvm_arch.config_lock. + */ +#define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) +#define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1) + u64 normal[KVM_ARM_ID_REG_NUM]; + + u64 midr_el1; + u64 revidr_el1; + u64 aidr_el1; + u64 ctr_el0; +}; + +static inline u64 *__vm_id_reg(struct kvm_vm_id_regs *id_regs, u32 reg) +{ + switch (reg) { + case sys_reg(3, 0, 0, 1, 0) ... sys_reg(3, 0, 0, 7, 7): + return &id_regs->normal[IDREG_IDX(reg)]; + case SYS_CTR_EL0: + return &id_regs->ctr_el0; + case SYS_MIDR_EL1: + return &id_regs->midr_el1; + case SYS_REVIDR_EL1: + return &id_regs->revidr_el1; + case SYS_AIDR_EL1: + return &id_regs->aidr_el1; + default: + WARN_ON_ONCE(1); + return NULL; + } +} + +#define kvm_read_vm_id_reg(kvm, reg) \ + ({ u64 __val = *__vm_id_reg(&(kvm)->arch.id_regs, reg); __val; }) + struct vcpu_reset_state { unsigned long pc; unsigned long r0; -- 2.53.0