From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.andi.de1.cc (mail.andi.de1.cc [178.238.236.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05664421F12 for ; Fri, 29 May 2026 18:36:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.238.236.174 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780079816; cv=none; b=nWVRVK7kmhV1l4OE0FUxxeSuYvLMvcsXBd0Z97NH2PYGXCFKBwBnLxNLLANOs77F5hexzp1O8YvWBo1cIStWoYFGtFXWQYg94+1ziBC5JjU1pxJ70GldO7zm7F2ybyYURNLahcTaiaseFCo2e3NvSATBFOYhA/IQr/3JOz3kXPA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780079816; c=relaxed/simple; bh=UhosB5pwAKD77gtwHtSYkMsVh9AJl/y9mur/vx7AW2k=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JsxmViW1P/OY/R5ODhaCy5hQZyEL+adMl1E15LzYQFNz5fANq0Zipe+zGuYhfpETFIASRTfF1Gy+UCk7X5U5UP9h9wTi71lhljFO/1dorrnljnuvNRjTFG04CgyQZW1F+2wVruA1IBL2WF6Gs13dK13vqk+3RkonmR4s6XJPsqs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=kemnade.info; spf=pass smtp.mailfrom=kemnade.info; dkim=pass (2048-bit key) header.d=kemnade.info header.i=@kemnade.info header.b=Y5ejxRfg; arc=none smtp.client-ip=178.238.236.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=kemnade.info Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=kemnade.info Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kemnade.info header.i=@kemnade.info header.b="Y5ejxRfg" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kemnade.info; s=20220719; h=References:In-Reply-To:Cc:From:Sender:Reply-To: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID; bh=sTmihkNHKEYjBALrV5BfEAzROK2od+s1ImGaDID6VEE=; b=Y5ejxRfgK5dhjxvejNXZfyZZ00 G5vwIbl4gpapBmptYtnvl8XzCqy+RRgJaaArYJuvbn9G4AsLpDGK6P5XEfUzb4e87DXrI0E3GjbII YKqLa4X70YAuUKXWUjrbFnmNCVGbcY3O6gG1G96gnxxUhZtlsUakIB3Qt5vmfJ6GJk/dRL5PUndKS KcmNNkY8Jpm6BFSEo06LzC1/0pafdkBmM/+g/VrFUYez7kcM/dSJd/r/HhT9Jlmsrh+PMg5ZSyxC+ Jx7jZhdN9gBjk2JtPpq79Th2I1gshMKWKQIgNVDFg5R7lkk4afGb58a32inKX3d0MRAJPwXCkZY6V in3kCpfA==; Date: Fri, 29 May 2026 20:34:24 +0200 From: Andreas Kemnade To: Tomi Valkeinen Cc: Marek Vasut , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dave Stevenson Subject: Re: [PATCH v3 07/13] drm/bridge: tc358762: Update comment about the number of lanes Message-ID: <20260529203424.72199881@kemnade.info> In-Reply-To: <20260513-tc358762-fixes-v3-7-6698b55008b9@ideasonboard.com> References: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> <20260513-tc358762-fixes-v3-7-6698b55008b9@ideasonboard.com> X-Mailer: Claws Mail 4.3.1 (GTK 3.24.49; aarch64-unknown-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 13 May 2026 16:10:16 +0300 Tomi Valkeinen wrote: > Update comment about the number of lanes. > > Signed-off-by: Tomi Valkeinen > --- > drivers/gpu/drm/bridge/tc358762.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc358762.c > index 7840ab3454f6..c5734c4df440 100644 > --- a/drivers/gpu/drm/bridge/tc358762.c > +++ b/drivers/gpu/drm/bridge/tc358762.c > @@ -306,7 +306,14 @@ static int tc358762_probe(struct mipi_dsi_device *dsi) > ctx->dev = dev; > ctx->pre_enabled = false; > > - /* TODO: Find out how to get dual-lane mode working */ > + /* > + * When using DSI clk for pixel clock (only mode supported in the driver), > + * the pclk is derived directly from the DSI byteclk via simple divider, > + * which is either 2 or 3. > + * The required divider can be calculated with bitspp / 8 / nlanes. Thus, > + * for RGB888, only nlanes = 1 works as nlanes = 2 would require divider > + * of 1.5. > + */ > dsi->lanes = 1; > dsi->format = MIPI_DSI_FMT_RGB888; > dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | > wondering: I am using lanes = 2 and RGB888. But I need to write something to SYSPLL3 register. Which somehow is sensitive to write to.... Do you have any information about that register? My dirty attic: https://github.com/akemnade/linux/blob/epson-7.1rc-panel-experiments-part-upstr/drivers/gpu/drm/panel/panel-bt2.c Regards, Andreas