From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBD081E260C for ; Sat, 30 May 2026 23:09:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780182563; cv=none; b=TXa0s0l3Vy9aFJqfm22gIcOj+fXmMC+lzhe5Hs60dwEG17jFPOILO1SnaMGRUepC4BuUHsl+RG3MQTGY2c7NOJiVc3z7PhLl0ABHwXYGxCYWXe4hZEL+/nuDzCCuCGLfEv6neVAGmuamKtWLpANnRMg5kdjqFd/nL7Px8RpYOGs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780182563; c=relaxed/simple; bh=NnrDjmZo1tNysHpVznTjHHrX+yCQZznnu87SuhObnrE=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=SPpThkU3chv26kGu4afF3sMshGLZbAXDm3urfhCPOjfO/4NdyhmeIgZLqr1x6OrvkTha4A/EbiLMDazwgYsl8C8uEKFnelt9ZkpoRX+j9q1KgCXb1G6ZND5vRyc3YQSCf0EmdbpFVuWwfy/MUVL3YjvuiM64ZqYQA9zDgIYHgnw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=o3MGoYVh; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="o3MGoYVh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A28E91F00893; Sat, 30 May 2026 23:09:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780182562; bh=NnrDjmZo1tNysHpVznTjHHrX+yCQZznnu87SuhObnrE=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=o3MGoYVhbNhpJKf7AATwAEPncmpcxzoiOH+vGUh8Xxd4rCypEpc3p7J1SpiF/Lybt 0waxmy1jbVRe+i5/qabeg+BBtl+fD7MHqG90AGm5AbtGlT9q0x/NqX1ETTH53LLVGW N+xjEOozkGUFlZDivC+F74LXXp5U4INqhw/M0D/ssK1yiOdRwdspfnIPQ9VYR4l1ex MhZAwNqSyvVUXf1dUOFlT5PcaPjYmUszBNkI72Lktwh6/wT+Hoonj4Ie04KzSgP+vD h3lskzxdkdGCQ8MTg3VpNTWZ6WvuJ+Lnbyy6A6JbbWm2tOa42SIezGKvvS+492mdyi ifpR0Kxzt/dTg== Date: Sun, 31 May 2026 00:09:17 +0100 From: Conor Dooley To: Qingwei Hu Cc: Vivian Wang , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Deepak Gupta , Pincheng Wang , Chunyan Zhang , Hui Wang , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Xu Lu , Guodong Xu Subject: Re: [PATCH v1] riscv: cpufeature: Add Zic64b ISA extension support Message-ID: <20260530-spoils-studied-d0858257c982@spud> References: <20260528141630.2741710-1-qingwei.hu@bytedance.com> <302dfaf7-4a38-408f-997e-68ed27de2341@iscas.ac.cn> <752F28EA-9255-4DBE-8007-F57947305D71@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="P7Cg7Win9lODgZ42" Content-Disposition: inline In-Reply-To: <752F28EA-9255-4DBE-8007-F57947305D71@bytedance.com> --P7Cg7Win9lODgZ42 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sat, May 30, 2026 at 11:36:11AM +0800, Qingwei Hu wrote: > Hi Vivian, >=20 > Thanks for the feedback. >=20 > > On May 29, 2026, at 11:14, Vivian Wang wrote: > >=20 > > On 5/28/26 22:16, Qingwei Hu wrote: > >> Zic64b describes a platform with 64-byte cache block sizes. It is a > >> mandatory part of RVA23U64, but a system may provide 64-byte CMO block > >> sizes without satisfying all profile requirements. > >>=20 > >> The ISA string parser currently ignores Zic64b because the extension is > >> not present in the cpufeature table. Add an ISA extension ID and table > >> entry for Zic64b so it can be reported in /proc/cpuinfo when firmware > >> advertises it. > >=20 > > I'd like to understand: What is the motivation to doing this, given that > > the very same information is already available as riscv,cbo*-block-size > > and hwprobe? >=20 > The motivation here is not to replace riscv,cbo*-block-size or hwprobe. > Those are still the right interfaces for software that needs the actual > CBO block size. >=20 > This is more about preserving the ISA extension name reported by > firmware. Some platforms report zic64b in the ISA string, but Linux > currently drops it because there is no cpufeature entry, so cpuinfo no > longer matches what firmware advertised. That makes profile/ISA-string > comparison tools a bit awkward. >=20 > So the patch only makes zic64b visible as a named ISA extension when > firmware reports it, while still validating it against any CBO block > sizes that firmware provides. >=20 > > If an extension is what we want to go with, then > > Documentation/devicetree/bindings/riscv/extensions.yaml also needs > > updating to match. >=20 > And yes, if we keep this direction, I agree extensions.yaml should be > updated in v2. And make sure that having zic64b makes the cbo*-block-size properties mandatory so that people don't confuse themselves and omit them and wonder why stuff doesn't work. Does zic64b mean that all of the zicbo* extensions are supported, or does it just mean that the supported ones use 64-byte block sizes? The answer to that will impact how you make the cbo*-block-size properties mandatory. Cheers, Conor. --P7Cg7Win9lODgZ42 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCahtuGQAKCRB4tDGHoIJi 0syPAP9KRd5XIBZvdBj2nRg0m6PQI/t3SEekzQwLGuGraNAdWwD9EBP16SE+83iH 8nJQrZ/lg+rA3Mag56Yhmz/ND1P4GQE= =NGXJ -----END PGP SIGNATURE----- --P7Cg7Win9lODgZ42--