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Sun, 31 May 2026 08:26:05 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Sun, 31 May 2026 17:26:00 +0200 Subject: [PATCH v4 07/11] m68k: mcf5441x: add CCR MISCCR2 bitfields Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260531-wip-stmark2-dac-v4-7-7e65ab4215dd@baylibre.com> References: <20260531-wip-stmark2-dac-v4-0-7e65ab4215dd@baylibre.com> In-Reply-To: <20260531-wip-stmark2-dac-v4-0-7e65ab4215dd@baylibre.com> To: Greg Ungerer , Geert Uytterhoeven , Steven King , Arnd Bergmann , Maxime Coquelin , Alexandre Torgue , Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko Cc: Greg Ungerer , linux-m68k@lists.linux-m68k.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-iio@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.15.2 From: Angelo Dureghello Add CCR MISCCR2 register bitfields. Signed-off-by: Angelo Dureghello --- Changes in v2: - add "iwyu" include for BIT and GENMASK - fix MCF_CCM_MISCCR2_PLL_MODE bitfield --- arch/m68k/include/asm/m5441xsim.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/m68k/include/asm/m5441xsim.h b/arch/m68k/include/asm/m5441xsim.h index 9ce2cbb05316..ea01c7753b7b 100644 --- a/arch/m68k/include/asm/m5441xsim.h +++ b/arch/m68k/include/asm/m5441xsim.h @@ -8,6 +8,8 @@ #ifndef m5441xsim_h #define m5441xsim_h +#include + #define CPU_NAME "COLDFIRE(m5441x)" #define CPU_INSTR_PER_JIFFY 2 #define MCF_BUSCLK (MCF_CLK / 2) @@ -145,6 +147,21 @@ #define MCF_CCM_SBFCR 0xec090022 #define MCF_CCM_FNACR 0xec090024 +/* Bit definitions and macros for MCF_CCM_MISCCR2 */ +#define MCF_CCM_MISCCR2_ULPI BIT(0) +#define MCF_CCM_MISCCR2_FB_HALF BIT(1) +#define MCF_CCM_MISCCR2_ADC3_EN BIT(2) +#define MCF_CCM_MISCCR2_ADC7_EN BIT(3) +#define MCF_CCM_MISCCR2_ADC_EN BIT(4) +#define MCF_CCM_MISCCR2_DAC0_SEL BIT(5) +#define MCF_CCM_MISCCR2_DAC1_SEL BIT(6) +#define MCF_CCM_MISCCR2_DCC_BYP BIT(7) +#define MCF_CCM_MISCCR2_PLL_MODE GENMASK(10, 8) +#define MCF_CCM_MISCCR2_SWT_SCR BIT(12) +#define MCF_CCM_MISCCR2_RGPIO_HALF BIT(13) +#define MCF_CCM_MISCCR2_DDR2_CLK BIT(14) +#define MCF_CCM_MISCCR2_EXTCLK_BYP BIT(15) + /* * UART module. */ -- 2.54.0