From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 394AC3E315F; Tue, 2 Jun 2026 13:25:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780406705; cv=none; b=EiUxS0wbj6ICWF2XRJEpA6HE3l1i22lxt8MSZSwS7MDX296pzex69Jy2ZKih2A+KuHEghwKNdspa+uLIS1wtM5pT4jHxQaUKK1KgV677mbWVayKrWYB+3aBAl+Ft/Hpli9x/yYdZAyCusmycktJEgDaChmHTG0SxUPYd6o6drwA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780406705; c=relaxed/simple; bh=oRZu3eePph574LLYQBblinNrMaZQAY/xVnLsaIDWonU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ievZT48SEmsUE9mONiinbKkE1AdBjHspOXU84wlnLk9UzS1ec+0OAlrbjvcUTlVKLVHt8c9Qh8mjB/eXO55GLbspItrS8Ty03qYrpgSNUET/AAGzIcOYccUOaFjmorK/COMq1XxauoNR8r+wobuEIs2BDRI9F3Vo6BOXW/D4kos= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=auBI5Yap; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="auBI5Yap" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1072BC2BD05; Tue, 2 Jun 2026 13:25:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780406705; bh=oRZu3eePph574LLYQBblinNrMaZQAY/xVnLsaIDWonU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=auBI5YapL5RRPxAszptq9runs2dn6/qEFl+Syjykq3zlU5/H0nkQS2luD1KYCCOK/ TA/FiJruchto84fIV7PSQED1nNe0qjVyhQDrTh1PC/QtHf0mQLRyRW39xSnNwB2N4I lzQycfY7Je1Ped7LB9mxotyyTkwMwvyFEzd3POSqKwRad5G/Wr3LzsJoZCXtN8V65n iDHCo7tKqDFD5L75+HZROOL9sC5Bo3g/tz7wIBIp+iOAFSjVlonaYiGOOPZdGY+kuY YN4HhxF+1GlVsLhokr0AeRVCQhkYIZTlB6RqIkK9tA1mxJ1X8YSIxly4eX9fUiziUC bexwePYD/OqQA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 021A5CD6E60; Tue, 2 Jun 2026 13:25:05 +0000 (UTC) From: Colin Huang via B4 Relay Date: Tue, 02 Jun 2026 21:25:03 +0800 Subject: [PATCH v3 8/9] ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260602-anacapa-devlop-phase-devicetree-v3-8-7c93c5df8d9b@gmail.com> References: <20260602-anacapa-devlop-phase-devicetree-v3-0-7c93c5df8d9b@gmail.com> In-Reply-To: <20260602-anacapa-devlop-phase-devicetree-v3-0-7c93c5df8d9b@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Andy Chung X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780406700; l=4631; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=kVrgdeyIILumAIqglDCa0K5zOenzetqMl+AfMwM1Ya4=; b=vrx/Pv6lGMAarGPzLbHcM8iiWG3M3J5vKfNJ0+D4MQZWFHQZINR/1+6BAtKn2yCa8ugglxR5B dMWPYeQuf6yAu2zzDv2bdnu7d5rigjtSBpDw8z17Olys/2mY07WFakF X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Andy Chung Add the mctp-controller property to enable frontend NIC management via PLDM over MCTP. Also add EEPROM device for NIC FRU and reorder the I2C virtual bus index accroding to the system silkscreen index. Signed-off-by: Andy Chung --- .../aspeed/aspeed-bmc-facebook-anacapa-evt1.dts | 98 ++++++++++++++++++---- 1 file changed, 80 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts index 29df10697613..5b6ce3c556fe 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts @@ -35,22 +35,22 @@ aliases { i2c33 = &i2c8mux0ch1; i2c34 = &i2c8mux0ch2; i2c35 = &i2c8mux0ch3; - i2c36 = &i2c10mux0ch0; - i2c37 = &i2c10mux0ch1; - i2c38 = &i2c10mux0ch2; - i2c39 = &i2c10mux0ch3; - i2c40 = &i2c10mux0ch4; - i2c41 = &i2c10mux0ch5; - i2c42 = &i2c10mux0ch6; - i2c43 = &i2c10mux0ch7; - i2c44 = &i2c11mux0ch0; - i2c45 = &i2c11mux0ch1; - i2c46 = &i2c11mux0ch2; - i2c47 = &i2c11mux0ch3; - i2c48 = &i2c11mux0ch4; - i2c49 = &i2c11mux0ch5; - i2c50 = &i2c11mux0ch6; - i2c51 = &i2c11mux0ch7; + i2c36 = &i2c11mux0ch5; + i2c37 = &i2c11mux0ch6; + i2c38 = &i2c11mux0ch7; + i2c39 = &i2c11mux0ch0; + i2c40 = &i2c11mux0ch1; + i2c41 = &i2c11mux0ch2; + i2c42 = &i2c11mux0ch3; + i2c43 = &i2c11mux0ch4; + i2c44 = &i2c10mux0ch1; + i2c45 = &i2c10mux0ch2; + i2c46 = &i2c10mux0ch3; + i2c47 = &i2c10mux0ch4; + i2c48 = &i2c10mux0ch5; + i2c49 = &i2c10mux0ch6; + i2c50 = &i2c10mux0ch7; + i2c51 = &i2c10mux0ch0; i2c52 = &i2c13mux0ch0; i2c53 = &i2c13mux0ch1; i2c54 = &i2c13mux0ch2; @@ -617,13 +617,17 @@ eeprom@56 { // R Bridge Board &i2c10 { status = "okay"; + multi-master; + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; i2c-mux@71 { compatible = "nxp,pca9548"; reg = <0x71>; #address-cells = <1>; #size-cells = <0>; - i2c-mux-idle-disconnect; i2c10mux0ch0: i2c@0 { reg = <0>; @@ -634,21 +638,45 @@ i2c10mux0ch1: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; }; i2c10mux0ch2: i2c@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; }; i2c10mux0ch3: i2c@3 { reg = <3>; #address-cells = <1>; #size-cells = <0>; + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; }; i2c10mux0ch4: i2c@4 { reg = <4>; #address-cells = <1>; #size-cells = <0>; + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; }; i2c10mux0ch5: i2c@5 { reg = <5>; @@ -694,38 +722,72 @@ i2c10mux0ch7: i2c@7 { // L Bridge Board &i2c11 { status = "okay"; + multi-master; + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; i2c-mux@71 { compatible = "nxp,pca9548"; reg = <0x71>; #address-cells = <1>; #size-cells = <0>; - i2c-mux-idle-disconnect; i2c11mux0ch0: i2c@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; + mctp-controller; + // FE NIC FRU + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; }; i2c11mux0ch1: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; }; i2c11mux0ch2: i2c@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; }; i2c11mux0ch3: i2c@3 { reg = <3>; #address-cells = <1>; #size-cells = <0>; + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; }; i2c11mux0ch4: i2c@4 { reg = <4>; #address-cells = <1>; #size-cells = <0>; + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; }; i2c11mux0ch5: i2c@5 { reg = <5>; -- 2.34.1