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Hopper and Blackwell GB10x need 2 MiB, while Blackwell GB20x needs 2 MiB + 128 KiB. These sizes diverge by family, so give Hopper and each Blackwell family its own framebuffer HAL and select the non-WPR heap size per chipset family. Reviewed-by: Eliot Courtney Signed-off-by: John Hubbard --- drivers/gpu/nova-core/fb.rs | 5 ++- drivers/gpu/nova-core/fb/hal.rs | 11 ++++-- drivers/gpu/nova-core/fb/hal/ga100.rs | 4 +++ drivers/gpu/nova-core/fb/hal/ga102.rs | 4 +++ drivers/gpu/nova-core/fb/hal/gb100.rs | 9 +++-- drivers/gpu/nova-core/fb/hal/gb202.rs | 52 +++++++++++++++++++++++++++ drivers/gpu/nova-core/fb/hal/gh100.rs | 50 ++++++++++++++++++++++++++ drivers/gpu/nova-core/fb/hal/tu102.rs | 8 +++++ 8 files changed, 136 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/nova-core/fb/hal/gb202.rs create mode 100644 drivers/gpu/nova-core/fb/hal/gh100.rs diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index d7a4dc944131..0aaee718c2c3 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -252,9 +252,8 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0, gsp_fw: &GspFirmware) -> Result< }; let heap = { - const HEAP_SIZE: u64 = u64::SZ_1M; - - FbRange(wpr2.start - HEAP_SIZE..wpr2.start) + let heap_size = u64::from(hal.non_wpr_heap_size()); + FbRange(wpr2.start - heap_size..wpr2.start) }; Ok(Self { diff --git a/drivers/gpu/nova-core/fb/hal.rs b/drivers/gpu/nova-core/fb/hal.rs index b45784ad5f2e..be9e75f990f0 100644 --- a/drivers/gpu/nova-core/fb/hal.rs +++ b/drivers/gpu/nova-core/fb/hal.rs @@ -14,6 +14,8 @@ mod ga100; mod ga102; mod gb100; +mod gb202; +mod gh100; mod tu102; pub(crate) trait FbHal { @@ -34,6 +36,9 @@ pub(crate) trait FbHal { /// Returns the amount of VRAM to reserve for the PMU. fn pmu_reserved_size(&self) -> u32; + /// Returns the non-WPR heap size for this chipset, in bytes. + fn non_wpr_heap_size(&self) -> u32; + /// Returns the FRTS size, in bytes. fn frts_size(&self) -> u64; } @@ -43,7 +48,9 @@ pub(super) fn fb_hal(chipset: Chipset) -> &'static dyn FbHal { match chipset.arch() { Architecture::Turing => tu102::TU102_HAL, Architecture::Ampere if chipset == Chipset::GA100 => ga100::GA100_HAL, - Architecture::Ampere | Architecture::Ada | Architecture::Hopper => ga102::GA102_HAL, - Architecture::BlackwellGB10x | Architecture::BlackwellGB20x => gb100::GB100_HAL, + Architecture::Ampere | Architecture::Ada => ga102::GA102_HAL, + Architecture::Hopper => gh100::GH100_HAL, + Architecture::BlackwellGB10x => gb100::GB100_HAL, + Architecture::BlackwellGB20x => gb202::GB202_HAL, } } diff --git a/drivers/gpu/nova-core/fb/hal/ga100.rs b/drivers/gpu/nova-core/fb/hal/ga100.rs index 0f5132aa9c31..af95f1bdd273 100644 --- a/drivers/gpu/nova-core/fb/hal/ga100.rs +++ b/drivers/gpu/nova-core/fb/hal/ga100.rs @@ -72,6 +72,10 @@ fn pmu_reserved_size(&self) -> u32 { super::tu102::pmu_reserved_size_tu102() } + fn non_wpr_heap_size(&self) -> u32 { + super::tu102::non_wpr_heap_size_tu102() + } + // GA100 is a special case where its FRTS region exists, but is empty. We // return a size of 0 because we still need to record where the region starts. fn frts_size(&self) -> u64 { diff --git a/drivers/gpu/nova-core/fb/hal/ga102.rs b/drivers/gpu/nova-core/fb/hal/ga102.rs index 17a2fef1ad44..e06dbb08349e 100644 --- a/drivers/gpu/nova-core/fb/hal/ga102.rs +++ b/drivers/gpu/nova-core/fb/hal/ga102.rs @@ -41,6 +41,10 @@ fn pmu_reserved_size(&self) -> u32 { super::tu102::pmu_reserved_size_tu102() } + fn non_wpr_heap_size(&self) -> u32 { + super::tu102::non_wpr_heap_size_tu102() + } + fn frts_size(&self) -> u64 { super::tu102::frts_size_tu102() } diff --git a/drivers/gpu/nova-core/fb/hal/gb100.rs b/drivers/gpu/nova-core/fb/hal/gb100.rs index c78027c26a9e..8d63350abf8a 100644 --- a/drivers/gpu/nova-core/fb/hal/gb100.rs +++ b/drivers/gpu/nova-core/fb/hal/gb100.rs @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 // SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. -//! Blackwell framebuffer HAL. +//! Blackwell GB10x framebuffer HAL. use kernel::{ prelude::*, @@ -20,7 +20,7 @@ struct Gb100; -const fn pmu_reserved_size_gb100() -> u32 { +pub(super) const fn pmu_reserved_size_gb100() -> u32 { usize_into_u32::<{ const_align_up(SZ_8M + SZ_16M + SZ_4K, Alignment::new::()).unwrap() }>( ) } @@ -48,6 +48,11 @@ fn pmu_reserved_size(&self) -> u32 { pmu_reserved_size_gb100() } + fn non_wpr_heap_size(&self) -> u32 { + // Non-WPR heap for GB10x (see Open RM: kgspGetNonWprHeapSize, GB100/GB102). + u32::SZ_2M + } + fn frts_size(&self) -> u64 { super::tu102::frts_size_tu102() } diff --git a/drivers/gpu/nova-core/fb/hal/gb202.rs b/drivers/gpu/nova-core/fb/hal/gb202.rs new file mode 100644 index 000000000000..542c1d7429e9 --- /dev/null +++ b/drivers/gpu/nova-core/fb/hal/gb202.rs @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + +//! Blackwell GB20x framebuffer HAL. + +use kernel::{ + prelude::*, + sizes::SizeConstants, // +}; + +use crate::{ + driver::Bar0, + fb::hal::FbHal, // +}; + +struct Gb202; + +impl FbHal for Gb202 { + fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { + super::ga100::read_sysmem_flush_page_ga100(bar) + } + + fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { + super::ga100::write_sysmem_flush_page_ga100(bar, addr); + + Ok(()) + } + + fn supports_display(&self, bar: &Bar0) -> bool { + super::ga100::display_enabled_ga100(bar) + } + + fn vidmem_size(&self, bar: &Bar0) -> u64 { + super::ga102::vidmem_size_ga102(bar) + } + + fn pmu_reserved_size(&self) -> u32 { + super::gb100::pmu_reserved_size_gb100() + } + + fn non_wpr_heap_size(&self) -> u32 { + // Non-WPR heap for GB20x (see Open RM: kgspGetNonWprHeapSize, GB202+). + u32::SZ_2M + u32::SZ_128K + } + + fn frts_size(&self) -> u64 { + super::tu102::frts_size_tu102() + } +} + +const GB202: Gb202 = Gb202; +pub(super) const GB202_HAL: &dyn FbHal = &GB202; diff --git a/drivers/gpu/nova-core/fb/hal/gh100.rs b/drivers/gpu/nova-core/fb/hal/gh100.rs new file mode 100644 index 000000000000..8f79c72b1823 --- /dev/null +++ b/drivers/gpu/nova-core/fb/hal/gh100.rs @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + +use kernel::{ + prelude::*, + sizes::SizeConstants, // +}; + +use crate::{ + driver::Bar0, + fb::hal::FbHal, // +}; + +struct Gh100; + +impl FbHal for Gh100 { + fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { + super::ga100::read_sysmem_flush_page_ga100(bar) + } + + fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { + super::ga100::write_sysmem_flush_page_ga100(bar, addr); + + Ok(()) + } + + fn supports_display(&self, bar: &Bar0) -> bool { + super::ga100::display_enabled_ga100(bar) + } + + fn vidmem_size(&self, bar: &Bar0) -> u64 { + super::ga102::vidmem_size_ga102(bar) + } + + fn pmu_reserved_size(&self) -> u32 { + super::tu102::pmu_reserved_size_tu102() + } + + fn non_wpr_heap_size(&self) -> u32 { + // Non-WPR heap for Hopper (see Open RM: kgspCalculateFbLayout_GH100). + u32::SZ_2M + } + + fn frts_size(&self) -> u64 { + super::tu102::frts_size_tu102() + } +} + +const GH100: Gh100 = Gh100; +pub(super) const GH100_HAL: &dyn FbHal = &GH100; diff --git a/drivers/gpu/nova-core/fb/hal/tu102.rs b/drivers/gpu/nova-core/fb/hal/tu102.rs index 1755bbc27866..62d9357987f7 100644 --- a/drivers/gpu/nova-core/fb/hal/tu102.rs +++ b/drivers/gpu/nova-core/fb/hal/tu102.rs @@ -44,6 +44,10 @@ pub(super) const fn pmu_reserved_size_tu102() -> u32 { 0 } +pub(super) const fn non_wpr_heap_size_tu102() -> u32 { + u32::SZ_1M +} + pub(super) const fn frts_size_tu102() -> u64 { u64::SZ_1M } @@ -71,6 +75,10 @@ fn pmu_reserved_size(&self) -> u32 { pmu_reserved_size_tu102() } + fn non_wpr_heap_size(&self) -> u32 { + non_wpr_heap_size_tu102() + } + fn frts_size(&self) -> u64 { frts_size_tu102() } -- 2.54.0