From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FCA03E5EFA; Tue, 2 Jun 2026 13:28:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780406926; cv=none; b=ah7NZcltZJpQoJMNxQaJDIPLyDnofQWDpDiYDgfvoYxQ4+/R1lj8+cWynMw5xqfmFD7nPygs3oBhoihWsyMsANfo483LPJQguTYZTP/0SePAGp4RWwT2gFBg1SJamqbwwFE3vpIKHoylEkNbiUG2XriRIqT8hz9kebGEbngYDpI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780406926; c=relaxed/simple; bh=iMNe4mkmJ5TZaA4toPowsDiOO+8246clif64nTzPRQs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UdeWnvNVT/JAHZqgZ7nCFWdk/O1997RPd8uw1N50mg/x03bXvf+MbhopMljaJhfG2hprKOBHCAmgofy89oU9zYChQEi7Llr2KhbXlcd+pKCYPgMmTLu52HI9K+121AgJ3CHglYNx8UzBQNTjxgzE2j5CRi23TijkKugvpDjUdIM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kKaipM2H; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kKaipM2H" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AB11A1F00893; Tue, 2 Jun 2026 13:28:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780406925; bh=+F8HoWQaPzi0AigpwIwaQzaOHhIjhtSUzJ3u8Xw8cto=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=kKaipM2Hrb+3Era4zpjZm1d4ziDA9WBPmfxfFWdih3cxJPCqppK9bxhzlbEWAiZqF +9AOE2s7U40ftdN8QIDowPOLP1ueF4Mse2R+T1jGUxNpfhCgq0QhjmOO62/erB9+Gx hLqS1bXSU2K4GSPh05CHdPJVWYxj+dqZdpIQRd/CZQNkxv5lQlkcem9SpAZURa+f52 ZtKFoQ5p5R3oEL1zE/CEclLEaZP8aVNjEShQaXozLpwaBcFpCUcxCUph2GOl7j3Q+j Y5RkwnZiQlfAraqx4uC8dXYFsVC/oy8aVg5uc9xYacZF9i9t2jGdmhg591+CYscweA vGfyDATco7vmA== From: Claudiu Beznea To: wsa+renesas@sang-engineering.com, tommaso.merciai.xr@bp.renesas.com, alexandre.belloni@bootlin.com, Frank.Li@nxp.com, p.zabel@pengutronix.de Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, Claudiu Beznea , stable@vger.kernel.org Subject: [PATCH v2 02/17] i3c: renesas: Restore STDBR and EXTBR registers on resume Date: Tue, 2 Jun 2026 16:28:09 +0300 Message-ID: <20260602132824.3541151-3-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260602132824.3541151-1-claudiu.beznea@kernel.org> References: <20260602132824.3541151-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Claudiu Beznea The Renesas RZ/G3S supports a power saving state where power to the most SoC componentes (including I3C) is lost. The STDBR and EXTBR are configured in initialization phase though the struct i3c_master_controller_ops::bus_init. Set them on resume function as well to keep the same state of the controller after a suspend with power loss and a similar initialization sequence as in bus_init. Fixes: e7218986319b ("i3c: renesas: Add suspend/resume support") Cc: stable@vger.kernel.org Reviewed-by: Frank Li Signed-off-by: Claudiu Beznea --- Changes in v2: - collected tags drivers/i3c/master/renesas-i3c.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/i3c/master/renesas-i3c.c b/drivers/i3c/master/renesas-i3c.c index 6e7ece2e0b4e..88a16efe096d 100644 --- a/drivers/i3c/master/renesas-i3c.c +++ b/drivers/i3c/master/renesas-i3c.c @@ -260,6 +260,7 @@ struct renesas_i3c { u32 dyn_addr; u32 i2c_STDBR; u32 i3c_STDBR; + u32 extbr; unsigned long rate; u8 addrs[RENESAS_I3C_MAX_DEVS]; struct renesas_i3c_xferqueue xferqueue; @@ -607,10 +608,9 @@ static int renesas_i3c_bus_init(struct i3c_master_controller *m) renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR); /* Extended Bit Rate setting */ - renesas_writel(i3c->regs, EXTBR, EXTBR_EBRLO(od_low_ticks) | - EXTBR_EBRHO(od_high_ticks) | - EXTBR_EBRLP(pp_low_ticks) | - EXTBR_EBRHP(pp_high_ticks)); + i3c->extbr = EXTBR_EBRLO(od_low_ticks) | EXTBR_EBRHO(od_high_ticks) | + EXTBR_EBRLP(pp_low_ticks) | EXTBR_EBRHP(pp_high_ticks); + renesas_writel(i3c->regs, EXTBR, i3c->extbr); renesas_writel(i3c->regs, REFCKCTL, REFCKCTL_IREFCKS(cks)); i3c->refclk_div = cks; @@ -1468,6 +1468,8 @@ static int renesas_i3c_resume_noirq(struct device *dev) goto err_tresetn; /* Re-store I3C registers value. */ + renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR); + renesas_writel(i3c->regs, EXTBR, i3c->extbr); renesas_writel(i3c->regs, REFCKCTL, REFCKCTL_IREFCKS(i3c->refclk_div)); renesas_writel(i3c->regs, MSDVAD, MSDVAD_MDYADV | -- 2.43.0