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[47.54.130.67]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8ccea2587a5sm134235176d6.46.2026.06.02.11.23.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 11:23:16 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1wUTlj-00000004Mz7-1ui4; Tue, 02 Jun 2026 15:23:15 -0300 Date: Tue, 2 Jun 2026 15:23:15 -0300 From: Jason Gunthorpe To: Mostafa Saleh Cc: Ashish Mhetre , will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, nicolinc@nvidia.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: Re: [PATCH v3 0/3] iommu/arm-smmu-v3: Tegra264 invalidation workaround Message-ID: <20260602182315.GH2487554@ziepe.ca> References: <20260601104845.995005-1-amhetre@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Jun 02, 2026 at 04:31:29PM +0000, Mostafa Saleh wrote: > On Mon, Jun 01, 2026 at 10:48:42AM +0000, Ashish Mhetre wrote: > > Nvidia Tegra264 SMMUs are affected by an erratum where a TLB entry can > > survive an invalidation that races with concurrent traffic targeting > > the same entry. The hardware-recommended software workaround is to > > issue every CFGI/TLBI command (each followed by CMD_SYNC) twice. The > > second issue must execute only after the first issue's CMD_SYNC has > > completed, giving the sequence: > > This seems quite intrusive, will the TLB entry survive if you push a > full invalidation instead? It's 36 lines and completely contained to the insides of the command sumbissions code?? Stuff like this is why I was guiding you to use the more code exactly as is for pkvm. Historically there have been many invalidation related errata, and invalidate twice seems to be a theme in fixing many of them. Jason