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Wed, 03 Jun 2026 07:21:07 -0700 (PDT) X-Received: by 2002:a17:903:4b50:b0:2c0:a373:89b9 with SMTP id d9443c01a7336-2c163a24bf2mr39122085ad.6.1780496466980; Wed, 03 Jun 2026 07:21:06 -0700 (PDT) Received: from hu-bvisredd-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c164f6d37esm41514955ad.9.2026.06.03.07.21.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jun 2026 07:21:06 -0700 (PDT) From: Vishnu Reddy Date: Wed, 03 Jun 2026 19:48:46 +0530 Subject: [PATCH v7 08/12] media: iris: Handle CPU_CS_SCIACMDARG3 register write via program bootup registers hook Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260603-glymur-v7-8-afaa55d11fe0@oss.qualcomm.com> References: <20260603-glymur-v7-0-afaa55d11fe0@oss.qualcomm.com> In-Reply-To: <20260603-glymur-v7-0-afaa55d11fe0@oss.qualcomm.com> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanimir Varbanov , Bjorn Andersson , Konrad Dybcio Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, Vishnu Reddy X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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Writing the default 0x1 causes the firmware to treat the VM count as 2. To avoid that write 0x0 to CPU_CS_SCIACMDARG3 as a Glymur platform specific. Signed-off-by: Vishnu Reddy --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 6 ++++++ drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 ++-- drivers/media/platform/qcom/iris/iris_vpu_register_defines.h | 1 + 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c index f07eaf4b3be2..65896d0c1f16 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -313,6 +313,11 @@ static int iris_vpu36_set_hwmode(struct iris_core *core) return ret; } +static void iris_vpu36_program_bootup_registers(struct iris_core *core) +{ + writel(0x0, core->reg_base + CPU_CS_SCIACMDARG3); +} + const struct vpu_ops iris_vpu3_ops = { .power_off_hw = iris_vpu3_power_off_hardware, .power_on_hw = iris_vpu_power_on_hw, @@ -346,6 +351,7 @@ const struct vpu_ops iris_vpu36_ops = { .power_on_hw = iris_vpu36_power_on_hw, .power_off_controller = iris_vpu35_vpu4x_power_off_controller, .power_on_controller = iris_vpu35_vpu4x_power_on_controller, + .program_bootup_registers = iris_vpu36_program_bootup_registers, .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode = iris_vpu36_set_hwmode, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index f35754ef53ed..5bbcad00ce09 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -26,7 +26,6 @@ #define QTBL_ENABLE BIT(0) #define QTBL_ADDR (CPU_CS_BASE_OFFS + 0x54) -#define CPU_CS_SCIACMDARG3 (CPU_CS_BASE_OFFS + 0x58) #define SFR_ADDR (CPU_CS_BASE_OFFS + 0x5C) #define UC_REGION_ADDR (CPU_CS_BASE_OFFS + 0x64) #define UC_REGION_SIZE (CPU_CS_BASE_OFFS + 0x68) @@ -67,6 +66,8 @@ static void iris_vpu_setup_ucregion_memory_map(struct iris_core *core) writel(value, core->reg_base + SFR_ADDR); } + writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3); + if (vpu_ops->program_bootup_registers) vpu_ops->program_bootup_registers(core); } @@ -78,7 +79,6 @@ int iris_vpu_boot_firmware(struct iris_core *core) iris_vpu_setup_ucregion_memory_map(core); writel(ctrl_init, core->reg_base + CTRL_INIT); - writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3); while (!ctrl_status && count < max_tries) { ctrl_status = readl(core->reg_base + CTRL_STATUS); diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h index e67d98b8c91e..de6a91041ea2 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h @@ -29,6 +29,7 @@ #define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C) #define CLEAR_XTENSA2HOST_INTR BIT(0) +#define CPU_CS_SCIACMDARG3 (CPU_CS_BASE_OFFS + 0x58) #define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148) #define HOST2XTENSA_INTR_ENABLE BIT(0) -- 2.34.1