From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 848053FBEA7; Wed, 3 Jun 2026 06:59:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780469944; cv=none; b=hZZe4gRN5vh5lpXxfKyEy5yYJXHu0u3Eqw4g7iEvuabHR4+rXg6OW/MauWraoJzgc3CSlO3KyTCKTyzLlP+audiEHIlJq/YZozRNqmxreBp+mEqxwRxsq1GzEIw3K1oN4zeiqECQFmNGrdE03IGvISH3xJEB8lNcaSyQoPJ/pjg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780469944; c=relaxed/simple; bh=gvdrgbWAjTx1CGi+PD6csR2l/AwBIyyRN8PqO/RwaYE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=KqRzmf+5TiUBIqf3NwmabiigiGLIQNm+DhuErSnyFFPdtFBFO16BugS20s6broBywHsmseeGZXRHF0e9trki+Ie/ROLIliDqJQBADQ2q1QSH6qGZWV6WTRxQEpXD7qvTAtVBiZHrYzFkEJxFxGO9p2ZU7EjHcN6P5DkipGFnmwU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=mmTwB6bR; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="mmTwB6bR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1780469940; x=1812005940; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=gvdrgbWAjTx1CGi+PD6csR2l/AwBIyyRN8PqO/RwaYE=; b=mmTwB6bRhUza/0RXwws8jEB2h35VN0sGVPOMIL1xjjHrA5CbZb5FtHMt Jhuk9zvzzSdRnRgi9IXUdhdLt2ff3RDTo9rEjRfoFVFjNi6N7P88XhLc7 l6X95sUyZLptaqhCqCR9RpP8O3PpMR2tZppBC06x7EWxKnB9Fed5n9y8p tDc3IVaeAOfzrGkzrojYhSL1ORSzB/xTSAwVQ5VrD6hXHt7pMCmvrPMDR 5xelWfE+KKBig2nHhETg4LjPfjMUUlH8ZxyIwCQAp9UF6/1/xXkhwWLKl nYGd9ijk9fJodEasQpTvGM3GWWaAZ4v0MlEZBV5DzADjA1tv3eA8YRdYV Q==; X-CSE-ConnectionGUID: kUVm4y77Qr6MH99eyG2lMA== X-CSE-MsgGUID: B9hFH3A1SeG0OffNweqGmg== X-IronPort-AV: E=Sophos;i="6.24,184,1774335600"; d="scan'208";a="67453796" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 02 Jun 2026 23:58:59 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 2 Jun 2026 23:58:59 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 2 Jun 2026 23:58:55 -0700 From: Balakrishnan Sambath Date: Wed, 3 Jun 2026 12:28:45 +0530 Subject: [PATCH v6 02/12] media: microchip-isc: fix WB offset and gain register field masking Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260603-microchip-isc-fixes-v6-2-8c3d7474a768@microchip.com> References: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> In-Reply-To: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: Laurent Pinchart , Kieran Bingham , Sakari Ailus , Balamanikandan Gunasundar , , , , "Balakrishnan Sambath" X-Mailer: b4 0.14.3 ISC_WB_O_* and ISC_WB_G_* pack two 13-bit fields per register. Sign extension from negative offsets corrupts the upper field. Mask both fields to 13 bits before packing. Fixes: 91b4e487b0c6 ("media: microchip: add ISC driver as Microchip ISC") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath --- .../media/platform/microchip/microchip-isc-base.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/drivers/media/platform/microchip/microchip-isc-base.c index a7cdc743fda7..45b94f1e89d8 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -61,18 +61,23 @@ static inline void isc_update_awb_ctrls(struct isc_device *isc) /* In here we set our actual hw pipeline config */ + /* + * Mask offset fields to 13 bits. Sign extension of negative s32 + * values would otherwise corrupt the adjacent field. + */ regmap_write(isc->regmap, ISC_WB_O_RGR, - ((ctrls->offset[ISC_HIS_CFG_MODE_R])) | - ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16)); + ((u32)ctrls->offset[ISC_HIS_CFG_MODE_R] & GENMASK(12, 0)) | + (((u32)ctrls->offset[ISC_HIS_CFG_MODE_GR] & GENMASK(12, 0)) << 16)); regmap_write(isc->regmap, ISC_WB_O_BGB, - ((ctrls->offset[ISC_HIS_CFG_MODE_B])) | - ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16)); + ((u32)ctrls->offset[ISC_HIS_CFG_MODE_B] & GENMASK(12, 0)) | + (((u32)ctrls->offset[ISC_HIS_CFG_MODE_GB] & GENMASK(12, 0)) << 16)); + /* Gains are 13-bit unsigned fields [12:0] and [28:16] */ regmap_write(isc->regmap, ISC_WB_G_RGR, - ctrls->gain[ISC_HIS_CFG_MODE_R] | - (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16)); + (ctrls->gain[ISC_HIS_CFG_MODE_R] & GENMASK(12, 0)) | + ((ctrls->gain[ISC_HIS_CFG_MODE_GR] & GENMASK(12, 0)) << 16)); regmap_write(isc->regmap, ISC_WB_G_BGB, - ctrls->gain[ISC_HIS_CFG_MODE_B] | - (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16)); + (ctrls->gain[ISC_HIS_CFG_MODE_B] & GENMASK(12, 0)) | + ((ctrls->gain[ISC_HIS_CFG_MODE_GB] & GENMASK(12, 0)) << 16)); } static inline void isc_reset_awb_ctrls(struct isc_device *isc) -- 2.34.1