From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4081F2F7478; Tue, 2 Jun 2026 23:30:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780443053; cv=none; b=XFSaxX+9wZymNLB74gO9rom8tyyc49ZZzgJEd7+1iGaboQS7DiMpDwZzuhAnmEug2xKONbGQ6Lga25zRDFb/BN1PBzGr24TcT5X1/PoqBg6krFzStMV8yrle5H7+3dwNKbWl4BIwx3gjVF5HJOiHFC6n5R8EUQXxSHzOCepg+uI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780443053; c=relaxed/simple; bh=0D8g4AImFTFvs5lsTS1IIcx/jjYEz1vDl3v4NBhoG1Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OcyZd0Bu0tB0vD8eKBpYjLJ40k4E3Nb++v5XXItppIhLkPzp7PEt3eifMZLGPDB5uirs6kNsXUr5kG5EMnoPSh/Tj16A4nEbfXrin5VHh6O8pN7mDCtbEM0Tg+A3s/IFcTMKs5Yz2UxY3znZaEl+iD0HFwJ4mKkl27s4M8BDJNk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Pf4hzHaI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Pf4hzHaI" Received: by smtp.kernel.org (Postfix) with ESMTPS id 017BBC2BCF5; Tue, 2 Jun 2026 23:30:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780443053; bh=0D8g4AImFTFvs5lsTS1IIcx/jjYEz1vDl3v4NBhoG1Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Pf4hzHaIP+IEKI7gTpVQQfQ+qsbhzxxq8y23A3D0Dcy+YdgBPUG3gUAIivAz57mtM 8vMDWK8dHjkUYoGSEphzZCT9pSXhVePYkW8gmWVv/YapcnvTOGnnJnrGJTMGLqk7WJ Rsi4nmhcsSfIeamVqvg7jXS2Dix1Y+ruHfHePIxXYjgo6CTF0fw30rc2/yihoByM2i DSGMdIG/iHFOq44imF+anQyzcYh92K+9BDzgNVbTRsaKby5MaJo++1XIQptmwP+/9J 3m2DFCrFn+ZonVsMj+fFBYkKFWggOFbbMr8IjMY2VHdJtHttgEmaoFydMH6i8sCYkj xAV7uOUAVOy0Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEC40CD6E64; Tue, 2 Jun 2026 23:30:52 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Wed, 03 Jun 2026 01:30:40 +0200 Subject: [PATCH v6 2/8] media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260603-qcom-cphy-v6-2-e50de0b557a8@ixit.cz> References: <20260603-qcom-cphy-v6-0-e50de0b557a8@ixit.cz> In-Reply-To: <20260603-qcom-cphy-v6-0-e50de0b557a8@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , "Dr. Git" , Cory Keitz , Loic Poulain Cc: Konrad Dybcio , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3582; i=david@ixit.cz; h=from:subject:message-id; bh=2iwXEDgsMZxXz7yxAHZuSfLV4jh0Xg07CX8XjfBaN+4=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBqH2eqzAg3D+4xv7/TiJT9BmF7mT4LRN59s3VjO lrOMm6H402JAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCah9nqgAKCRBgAj/E00kg ctyzD/4ipYEqsPBUfgonbaz2EJKf5OvTAeYOqpgq8whhJs98wHaX9GIzCE9hvdI5oZodg+mx0gd pNlbHXKgra3z2sNPKraoDNE9e5iY+eqpX+QwtU6JS7K7E2e5m2CWs9MEowMEmDrZbbnaTGIKQti FqXOPYyS6JMzXEnA8g7bVPo4SQCUVEhMfrsuWV6cxh1u2FQS2b8l96J9/6NLTEb1kLnJA1MY5f2 wqcDAbn6OTu7mywLaOtin0k9c0qTL/pZ8wdvN7LDvsgmEMsIBX1zxGLnT/f8XviTpQmPMS253HB KXllsI/oy5bJ+jWVBYSuoYzaPJTPU6dPxTnbVsPjesbX7wwz8k1MlbbK5N1LXCb0w0+ccW5W5i4 OBrTEZTiaZIu6JGtqYmJzeVqMVN6nplADe70/dWtM+fGKXhJXfDiqit7a7QgNUFRxLL8kB1Pqxn FDDxhJOXCd835HxSQSFoqMiZHdWz7XEDyTwEW1MQ6dRDNfsY3kZTSlXh24FUQ9cZ+SumSKIdH16 PUeQX6LqsLiIz23cov0uRo6GjAe/Bjpfy263Z3mDrqObisHZsOZEeMGvvWXui/y72tIO9Bc1zmL 4jGtoyl+GiUCT1caSg+mFd1iNeadH7c8EEFurqat3keEUfAMIb3FmOy/N3PnHY5KgfH70Vg32cN O23vZV9IVznw0cQ== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg So far, only D-PHY mode was supported, which uses even bits when enabling or masking lanes. For C-PHY configuration, the hardware instead requires using the odd bits. Since there can be unrecognized configuration allow returning failure. Reviewed-by: Bryan O'Donoghue Acked-by: Cory Keitz Reviewed-by: Bryan O'Donoghue Signed-off-by: David Heidelberg --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 39 +++++++++++++++++----- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index dac8d2ecf7995..15876eb973718 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -9,16 +9,17 @@ */ #include "camss.h" #include "camss-csiphy.h" #include #include #include +#include #define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n)) #define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG (BIT(7) | BIT(6)) #define CSIPHY_3PH_LNn_CFG2(n) (0x004 + 0x100 * (n)) #define CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT BIT(3) #define CSIPHY_3PH_LNn_CFG3(n) (0x008 + 0x100 * (n)) #define CSIPHY_3PH_LNn_CFG4(n) (0x00c + 0x100 * (n)) #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS 0xa4 @@ -1108,23 +1109,32 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, writel_relaxed(val, csiphy->base + r->reg_addr); if (r->delay_us) udelay(r->delay_us); } } static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg) { - u8 lane_mask; - int i; + u8 lane_mask = 0; - lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; + switch (lane_cfg->phy_cfg) { + case V4L2_MBUS_CSI2_CPHY: + for (int i = 0; i < lane_cfg->num_data; i++) + lane_mask |= BIT(lane_cfg->data[i].pos + 1); + break; + case V4L2_MBUS_CSI2_DPHY: + lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; - for (i = 0; i < lane_cfg->num_data; i++) - lane_mask |= 1 << lane_cfg->data[i].pos; + for (int i = 0; i < lane_cfg->num_data; i++) + lane_mask |= BIT(lane_cfg->data[i].pos); + break; + default: + break; + } return lane_mask; } static bool csiphy_is_gen2(u32 version) { bool ret = false; @@ -1155,19 +1165,32 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy, struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg; struct csiphy_device_regs *regs = csiphy->regs; u8 settle_cnt; u8 val; int i; settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); - val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; - for (i = 0; i < c->num_data; i++) - val |= BIT(c->data[i].pos * 2); + val = 0; + + switch (c->phy_cfg) { + case V4L2_MBUS_CSI2_CPHY: + for (i = 0; i < c->num_data; i++) + val |= BIT((c->data[i].pos * 2) + 1); + break; + case V4L2_MBUS_CSI2_DPHY: + val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; + + for (i = 0; i < c->num_data; i++) + val |= BIT(c->data[i].pos * 2); + break; + default: + WARN_ONCE(1, "Unsupported bus type %d!\n", c->phy_cfg); + } writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 5)); val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B; writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6)); -- 2.53.0