From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 749153E51DA for ; Wed, 3 Jun 2026 03:08:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.53 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780456104; cv=none; b=ff9/btd3wr1XRF5knFlONd7n4iV6h1/i/WJ7uV7Nhe85hjSLDEAXs3zeOZLspzGSXy/JlB2TsWYcysmnmt4r8PGAwfFkOIXdaJcaCnSa9FC4msnrEDOUATSHbosnzVOhKIkXx3l2EhHx1PwXR6HwDizXry5z3gnlG4ECa4mWxAE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780456104; c=relaxed/simple; bh=O9qpMQO4gyEQEH9XMabcCwD7cgwVapAp8DL4oHFYuDU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CstaV/MOzrVHfk1Ot5Wxdd4DUOYLXanHpRND73nErJKOho1i5Jv7kRVhjVfKqcOA9/dqFG0LeKbW2cxA6zYzySdukyduKQfvU2OPGyuxKla1DSAjOBUmCmnoBDrfjjy6jmJS78x1iPV4Ig2Wl0WnaJ222aXxEEbRQSQXX778bJs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=QYxgE5xU; arc=none smtp.client-ip=209.85.216.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QYxgE5xU" Received: by mail-pj1-f53.google.com with SMTP id 98e67ed59e1d1-36ad15213fbso6056541a91.0 for ; Tue, 02 Jun 2026 20:08:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1780456102; x=1781060902; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LZKzG1cjjYqCrg5ftXH0wOdwx3jBheILV4yoP9XwymI=; b=QYxgE5xUl5mcE9jXDuNnMYL4wZ3rXTFkuo4GRdwcOQvqT9HTIZMMXQ06k4D/6MZRPX Xz/+2hax99ZxH9LW4HeVc7Wb7kB699RcaYyfuHFch/dchz9iPG2c1TXOaZi5hx1WNCYg PuMvtdWRvDYtgVkMWAxkPengl73UHBqm9gt7rzMjJ6XTfeHPjRpth2JHDd9S8WmnzoqX CQ26Q6PDKRdNIT2KGJhFzm9yJD/YGrQkanKvAQGcDbbFAx1d/FmXlKfkPq8VcrfyKjRa NO4snquXlmL6zYdRvXWzTuy/a2GAMrS00xJ7v5LGCvpn73tEl4Slffc9+uK20KLnVL+i sZjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780456102; x=1781060902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=LZKzG1cjjYqCrg5ftXH0wOdwx3jBheILV4yoP9XwymI=; b=s7aRXr1T/HNxq2uc1LcMuYAcomg/3s/9y+MIWYHBKFKYPDuid4/lrqa6ICPleSc2/B qh7AIymbvkHwBKuUghcvNPeIZb+HAD9Uu91GWdgfH0Eed7T5xja+Px5oG2D1Yau/Otp3 y6QcHchDoWO3X50YHMTGjz0axu4+OdNyh3q76Rci19et9gdycwzc/yk8RokEUPMwsgRe w+tdvDo8/Xao6N6BVOTr/cRKjXQeAjuQ7TcMzRFbl4z3nPpNKHUe/K8B0nv0V6NKWoDl bZEgpwp2BzKO+aBM4WpvGAUqRsuYkP4V+kWK48mow1A2yinhFZtOVckFNwsIfW+mWTCf 6uCg== X-Forwarded-Encrypted: i=1; AFNElJ/5IcLKFz6Mk/nOASIjkMrIsEjwO8QhzBTUG3HsSuyyrMlBXKOYbfF1KBXWqdCjqjFyMJ6ETMizJoM/sUQ=@vger.kernel.org X-Gm-Message-State: AOJu0YzdRPnLcOkzC5cOlGrenBqSu8IiXun8tEm2QfABziCEmvApkexH PLAG7eTeU2ET+HtuTqer/zBl3LE72QDvxOYse89ACx/Jjb87/7qhK6xO0MwfLsYP X-Gm-Gg: Acq92OEzxtkhExf5JDyYoKtKyrF/MnKD9jW2wQ9XYGDSORdlIEtQU3C7PRkzeNbxHaT qgwAETAoatU9Y8sncGRJXgghpvHIJsvKJtSe1ExxufeENoAipZH1BuhFAXTBURRFfQnUO0U/eoK w1vg/C4KNh6N+9W/UipoFAFsJ/Q2y6VulijyFwyqjqC5ByXNWklnwetx7cjZh8FCeJgyA0rG8Da O/2Uqz978m9DSrZtpmZzIVYCisxDEzf4icBsSWbaiyDN3SghvMXGOEUKQe90vKOgp9kv70ikynd a0ZjNvM+QP+VSVNos3uQEp+88IcLxaGElenZg1K6+dy6VPksQz9u8s4/0y5rceQY2KnDu7PS2ca GxaMPinlGNmsBbXsV1SgOhdTTwoNMAvXDDlV2+kdYSLN9RzBONMWoouGet/juIa8c0IrijTpvIM zLQtKL0PjMmo/PpvFzWQBDh66kUIN71hc8forDeR3KsAxxBMTU5dbP6Da4PfEVlQD85IJeiFeYG UT8H3C6YqBFL0GmtaEks3yFh4MXMc2s35H2rY8qk/tEkw== X-Received: by 2002:a17:90b:38ce:b0:36c:e254:4d5 with SMTP id 98e67ed59e1d1-36e306482e3mr1303320a91.4.1780456101691; Tue, 02 Jun 2026 20:08:21 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d:7285:c2ff:fe45:8a32]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36e0a186741sm1247102a91.8.2026.06.02.20.08.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 20:08:20 -0700 (PDT) From: Rosen Penev To: dmaengine@vger.kernel.org Cc: Peter Ujfalusi , Vinod Koul , Frank Li , Kees Cook , "Gustavo A. R. Silva" , Haotian Zhang , Tony Lindgren , Russell King , linux-kernel@vger.kernel.org (open list), linux-hardening@vger.kernel.org (open list:KERNEL HARDENING (not covered by other areas):Keyword:\b__counted_by(_le|_be|_ptr)?\b) Subject: [PATCHv3 5/8] dmaengine: ti: omap-dma: disable IRQs on probe failure Date: Tue, 2 Jun 2026 20:07:51 -0700 Message-ID: <20260603030754.288757-6-rosenp@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260603030754.288757-1-rosenp@gmail.com> References: <20260603030754.288757-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The probe failure paths after IRQ setup free channel state while hardware interrupts can still be enabled. A concurrent interrupt can then walk lch_map[] and access channel memory that teardown is releasing. Disable IRQENABLE_L1 and clear irq_enable_mask under irq_lock before teardown, then read IRQENABLE_L1 back to flush the posted write. Guard the L1 accesses for legacy platforms where that register is not mapped. Fixes: 7bedaa553760 ("dmaengine: add OMAP DMA engine driver") Cc: stable@vger.kernel.org Assisted-by: Codex:GPT-5 Signed-off-by: Rosen Penev --- drivers/dma/ti/omap-dma.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/dma/ti/omap-dma.c b/drivers/dma/ti/omap-dma.c index cef4e3a38b04..61a935660341 100644 --- a/drivers/dma/ti/omap-dma.c +++ b/drivers/dma/ti/omap-dma.c @@ -1811,6 +1811,13 @@ static int omap_dma_probe(struct platform_device *pdev) if (rc) { pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n", rc); + if (!omap_dma_legacy(od)) { + spin_lock_irq(&od->irq_lock); + od->irq_enable_mask = 0; + omap_dma_glbl_write(od, IRQENABLE_L1, 0); + spin_unlock_irq(&od->irq_lock); + omap_dma_glbl_read(od, IRQENABLE_L1); + } if (od->ll123_supported) dma_pool_destroy(od->desc_pool); omap_dma_free(od); @@ -1828,6 +1835,13 @@ static int omap_dma_probe(struct platform_device *pdev) if (rc) { pr_warn("OMAP-DMA: failed to register DMA controller\n"); dma_async_device_unregister(&od->ddev); + if (!omap_dma_legacy(od)) { + spin_lock_irq(&od->irq_lock); + od->irq_enable_mask = 0; + omap_dma_glbl_write(od, IRQENABLE_L1, 0); + spin_unlock_irq(&od->irq_lock); + omap_dma_glbl_read(od, IRQENABLE_L1); + } if (od->ll123_supported) dma_pool_destroy(od->desc_pool); omap_dma_free(od); -- 2.54.0