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FlexCAN IP integration on S32N79 SoC uses two interrupts: - one for mailboxes 0-127 - one for signaling bus errors and device state changes Co-developed-by: Andra-Teodora Ilie Signed-off-by: Andra-Teodora Ilie Co-developed-by: Larisa Grigore Signed-off-by: Larisa Grigore Signed-off-by: Ciprian Marian Costea --- drivers/net/can/flexcan/flexcan-core.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/net/can/flexcan/flexcan-core.c b/drivers/net/can/flexcan/flexcan-core.c index 23ddf7910641..9ae0d9eb4ccc 100644 --- a/drivers/net/can/flexcan/flexcan-core.c +++ b/drivers/net/can/flexcan/flexcan-core.c @@ -397,6 +397,15 @@ static const struct flexcan_devtype_data nxp_s32g2_devtype_data = { FLEXCAN_QUIRK_SECONDARY_MB_IRQ, }; +static const struct flexcan_devtype_data nxp_s32n_devtype_data = { + .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | + FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX | + FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_FD | + FLEXCAN_QUIRK_SUPPORT_ECC | FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | + FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR | + FLEXCAN_QUIRK_IRQ_BERR, +}; + static const struct can_bittiming_const flexcan_bittiming_const = { .name = DRV_NAME, .tseg1_min = 4, @@ -2232,6 +2241,7 @@ static const struct of_device_id flexcan_of_match[] = { { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, }, { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, }, { .compatible = "nxp,s32g2-flexcan", .data = &nxp_s32g2_devtype_data, }, + { .compatible = "nxp,s32n79-flexcan", .data = &nxp_s32n_devtype_data, }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, flexcan_of_match); -- 2.43.0