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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-137f553ab33sm2870659c88.10.2026.06.03.18.33.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jun 2026 18:33:25 -0700 (PDT) From: Matthew Leung Date: Thu, 04 Jun 2026 01:32:56 +0000 Subject: [PATCH v2 02/10] phy: qcom-qmp: qserdes-com: Add v10 register offsets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260604-hawi-phy-pcie-v2-2-be908d3560db@oss.qualcomm.com> References: <20260604-hawi-phy-pcie-v2-0-be908d3560db@oss.qualcomm.com> In-Reply-To: <20260604-hawi-phy-pcie-v2-0-be908d3560db@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matthew Leung X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780536795; l=3231; i=matthew.leung@oss.qualcomm.com; s=20260428; h=from:subject:message-id; bh=mETc0jlTLmI462gvqIk7CFJGzUvc8N7VZDu2GYCH5bo=; b=qqVc0bY8pU7gFmiGPp5xHwp7Zlvwef4gHCmv+0IeIt8Ts2r1ZkxnvOk3gn9PQ3gt852XAThTm IHTv7mfvS6OCbni1Rr8wZANCDE8naKzYZzg8v/8bopWaLoECLysAUDP X-Developer-Key: i=matthew.leung@oss.qualcomm.com; a=ed25519; pk=aT25ggJo5PMHLN9N+TsZ3s/BVU++kEYuiFebPWe21+o= X-Proofpoint-GUID: QPSqDyZQ7jG7hg3TxU53pS67ci_eS6Qe X-Authority-Analysis: v=2.4 cv=M8h97Sws c=1 sm=1 tr=0 ts=6a20d5e8 cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=MN0C-abDVP1yrleAEAUA:9 a=QEXdDO2ut3YA:10 a=vBUdepa8ALXHeOFLBtFW:22 X-Proofpoint-ORIG-GUID: QPSqDyZQ7jG7hg3TxU53pS67ci_eS6Qe X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA0MDAxMiBTYWx0ZWRfXyTv1Tc8xlMKA JLS/phJb4dxO4Q4DLihiLQqvwpV4wKhabwPP30VOZXybLIwTVhOMmpHW2GV+N8UH61zd8iH39sX jvGYwbPEVztd/IE4xg6o7iAAgBgTMrrJuQqN+4z61iPW5j7daFDwtep4cfNSqNm1iS/rmlFbXzx +HxuVbBEvlZxaRxhjgL/ao0UcTEa8C1ctF/O+5FsZBOW3W3WI35IE2pB2AiarQqlPJjhYpR6C6G 60ere6hQWaXHpJrdn9iG9OzZIlhcYqjEwpgbd5BMy//yme7jLZeebVygLanlW8ubom6z/kv3HCl tR/UD5qYoa3bItMSx/0GA+tSoVPJYv9P3WePKTBVoz8SAg6fj/RKBi4lUUo00EO+5iDjVeGaPkz V8vqUeqKe5F/mvSxG3b4evpzNsEQ6enY7YbVdtOxA0Epgk5G6pXb7KcWl0jdybLDuVbiF/HEeLT sgXvQgk1oHJPZr0bu/w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-04_01,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 malwarescore=0 suspectscore=0 spamscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606040012 Hawi SoC uses v10 register definitions for PCIe Gen3 x2. Add the new QSERDES-COM offsets in a dedicated header file. Signed-off-by: Matthew Leung --- .../phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h | 49 ++++++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 2 + 2 files changed, 51 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h new file mode 100644 index 000000000000..09199e7b4aac --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_COM_V10_H_ +#define QCOM_PHY_QMP_QSERDES_COM_V10_H_ + +/* Only for QMP V10 PHY - QSERDES COM registers */ +#define QSERDES_V10_COM_SSC_STEP_SIZE1_MODE1 0x00 +#define QSERDES_V10_COM_SSC_STEP_SIZE2_MODE1 0x04 +#define QSERDES_V10_COM_CP_CTRL_MODE1 0x10 +#define QSERDES_V10_COM_PLL_RCTRL_MODE1 0x14 +#define QSERDES_V10_COM_PLL_CCTRL_MODE1 0x18 +#define QSERDES_V10_COM_CORECLK_DIV_MODE1 0x1c +#define QSERDES_V10_COM_LOCK_CMP1_MODE1 0x20 +#define QSERDES_V10_COM_LOCK_CMP2_MODE1 0x24 +#define QSERDES_V10_COM_DEC_START_MODE1 0x28 +#define QSERDES_V10_COM_DIV_FRAC_START1_MODE1 0x30 +#define QSERDES_V10_COM_DIV_FRAC_START2_MODE1 0x34 +#define QSERDES_V10_COM_DIV_FRAC_START3_MODE1 0x38 +#define QSERDES_V10_COM_HSCLK_SEL_1 0x3c +#define QSERDES_V10_COM_SSC_STEP_SIZE1_MODE0 0x60 +#define QSERDES_V10_COM_SSC_STEP_SIZE2_MODE0 0x64 +#define QSERDES_V10_COM_CP_CTRL_MODE0 0x70 +#define QSERDES_V10_COM_PLL_RCTRL_MODE0 0x74 +#define QSERDES_V10_COM_PLL_CCTRL_MODE0 0x78 +#define QSERDES_V10_COM_LOCK_CMP1_MODE0 0x80 +#define QSERDES_V10_COM_LOCK_CMP2_MODE0 0x84 +#define QSERDES_V10_COM_DEC_START_MODE0 0x88 +#define QSERDES_V10_COM_DIV_FRAC_START1_MODE0 0x90 +#define QSERDES_V10_COM_DIV_FRAC_START2_MODE0 0x94 +#define QSERDES_V10_COM_DIV_FRAC_START3_MODE0 0x98 +#define QSERDES_V10_COM_BG_TIMER 0xbc +#define QSERDES_V10_COM_SSC_EN_CENTER 0xc0 +#define QSERDES_V10_COM_SSC_PER1 0xcc +#define QSERDES_V10_COM_SSC_PER2 0xd0 +#define QSERDES_V10_COM_CLK_ENABLE1 0xe0 +#define QSERDES_V10_COM_SYS_CLK_CTRL 0xe4 +#define QSERDES_V10_COM_PLL_IVCO 0xf4 +#define QSERDES_V10_COM_SYSCLK_EN_SEL 0x110 +#define QSERDES_V10_COM_LOCK_CMP_EN 0x120 +#define QSERDES_V10_COM_VCO_TUNE_MAP 0x140 +#define QSERDES_V10_COM_CLK_SELECT 0x164 +#define QSERDES_V10_COM_CORE_CLK_EN 0x170 +#define QSERDES_V10_COM_CMN_CONFIG_1 0x174 +#define QSERDES_V10_COM_ADDITIONAL_MISC_3 0x1bc + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index a873bdd7bffe..3ac5af7cde6a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -39,6 +39,8 @@ #include "phy-qcom-qmp-qserdes-txrx-v8.h" #include "phy-qcom-qmp-qserdes-lalb-v8.h" +#include "phy-qcom-qmp-qserdes-com-v10.h" + #include "phy-qcom-qmp-qserdes-pll.h" #include "phy-qcom-qmp-pcs-v2.h" -- 2.34.1