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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-137f553ab33sm2870659c88.10.2026.06.03.18.33.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jun 2026 18:33:28 -0700 (PDT) From: Matthew Leung Date: Thu, 04 Jun 2026 01:32:58 +0000 Subject: [PATCH v2 04/10] phy: qcom-qmp: pcs: Add v10 register offsets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260604-hawi-phy-pcie-v2-4-be908d3560db@oss.qualcomm.com> References: <20260604-hawi-phy-pcie-v2-0-be908d3560db@oss.qualcomm.com> In-Reply-To: <20260604-hawi-phy-pcie-v2-0-be908d3560db@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matthew Leung X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780536795; l=1794; i=matthew.leung@oss.qualcomm.com; s=20260428; h=from:subject:message-id; bh=cIrdj8/8qr+RDIhnZn+O7Cu+D6iGtXuFpw2ZdlFjXfY=; b=c6mBXCFpB6UsMq03JTTOU5Ckldp+W9UICY4nsLzcYP1H1ervM9SbUDwq8/pltZxG6OW6CT+9w SHHiFgKUtWrCFIRuLbLmY9uNsfsrzrdrE9G+/NQaM4UcjhMfkew5l/6 X-Developer-Key: i=matthew.leung@oss.qualcomm.com; a=ed25519; pk=aT25ggJo5PMHLN9N+TsZ3s/BVU++kEYuiFebPWe21+o= X-Proofpoint-GUID: Zq8iXvO69Cv22TAjs7lHOn1pUER_Luko X-Authority-Analysis: v=2.4 cv=XK0AjwhE c=1 sm=1 tr=0 ts=6a20d5ea cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=TapfYG-AjLmxlko4O74A:9 a=QEXdDO2ut3YA:10 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA0MDAxMiBTYWx0ZWRfX/hDzU3f2WviO HRNAiDr/KjVNqC204CdE65P37IeMQAXJvnkDOUjZxQrHHYk+iZcGoUX2PPaUhigahDsd7L20soo RJpXsxP4vneMH+GhUisCOOgaSkSY4MrJGcRc5hjlO0IFc/3gXoIWnzZGRxtf3wJc4uJ/G2vLr2F PtH2bZ3lPHlM1psEQ+B3mhGM6JjY+MmvI/l/hUHamli71rSoj6hUgNP5bK2Mpt+Xbw5odhyUVS7 F8ypjtA5AnNYoygGhPoG+VgvyU0NEXuT9p1B5WlOIZ69CkuMUuqWHedcZz78zz49CAB9T9IyAO6 zh9qN6VnUFNlsADaHXT83x+zkUmup3/BDyENHUG+jrdHr6tuLIsmjwRXCAJHjkj8rs0sNN7AJUQ mqxX8f3Pcxk6LEZDsXX8qNdNPhxOY8CoWvyGc2l6vYh7c21mcb7WEFADEwCGGAcppSm5oJ0HjJU NeuMAGJaPXb8OjFyDcg== X-Proofpoint-ORIG-GUID: Zq8iXvO69Cv22TAjs7lHOn1pUER_Luko X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-04_01,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 phishscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606040012 Hawi SoC bumps up the HW version of QMP phy to v10 for PCIe Gen3 x2. Add the new PCS offsets in a dedicated header file. Signed-off-by: Matthew Leung --- drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h | 22 ++++++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 2 ++ 2 files changed, 24 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h new file mode 100644 index 000000000000..6faca6d8736a --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef QCOM_PHY_QMP_PCS_V10_H_ +#define QCOM_PHY_QMP_PCS_V10_H_ + +/* Only for QMP V10 PHY - USB/PCIe PCS registers */ +#define QPHY_V10_PCS_SW_RESET 0x000 +#define QPHY_V10_PCS_PCS_STATUS1 0x014 +#define QPHY_V10_PCS_POWER_DOWN_CONTROL 0x040 +#define QPHY_V10_PCS_START_CONTROL 0x044 +#define QPHY_V10_PCS_REFGEN_REQ_CONFIG1 0x0dc +#define QPHY_V10_PCS_G12S1_TXDEEMPH_M6DB 0x168 +#define QPHY_V10_PCS_G3S2_PRE_GAIN 0x170 +#define QPHY_V10_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_V10_PCS_RATE_SLEW_CNTRL1 0x198 +#define QPHY_V10_PCS_PCS_TX_RX_CONFIG 0x1d0 +#define QPHY_V10_PCS_EQ_CONFIG2 0x1e4 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 76ac72410d31..7af77572970e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -68,6 +68,8 @@ #include "phy-qcom-qmp-pcs-v8_50.h" +#include "phy-qcom-qmp-pcs-v10.h" + /* QPHY_SW_RESET bit */ #define SW_RESET BIT(0) /* QPHY_POWER_DOWN_CONTROL */ -- 2.34.1