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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-137f553ab33sm2870659c88.10.2026.06.03.18.33.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jun 2026 18:33:35 -0700 (PDT) From: Matthew Leung Date: Thu, 04 Jun 2026 01:33:03 +0000 Subject: [PATCH v2 09/10] phy: qcom-qmp: pcs-pcie: Add v10.60 register offsets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260604-hawi-phy-pcie-v2-9-be908d3560db@oss.qualcomm.com> References: <20260604-hawi-phy-pcie-v2-0-be908d3560db@oss.qualcomm.com> In-Reply-To: <20260604-hawi-phy-pcie-v2-0-be908d3560db@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matthew Leung X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780536795; l=2258; i=matthew.leung@oss.qualcomm.com; s=20260428; h=from:subject:message-id; bh=F00WY5r3KpYlfjir5reJlgcKGKiWQ/l5Y3iLOGo4EiY=; b=9k9W1PbNAjQCFOz1jM9h88Z49vdjzddVAvYJrHWcjCPTa+RtCtE5TRBw+dR7XgbiegtN0XSJo 8k739u9GzfnAn2ovtmbmsR69fWTwLxUERUUB0Fn+nX7Y15hsM+7bCg6 X-Developer-Key: i=matthew.leung@oss.qualcomm.com; a=ed25519; pk=aT25ggJo5PMHLN9N+TsZ3s/BVU++kEYuiFebPWe21+o= X-Proofpoint-GUID: QteqWyqYzxaNfZ6wM4zNzlchX9ygtr8k X-Authority-Analysis: v=2.4 cv=XK0AjwhE c=1 sm=1 tr=0 ts=6a20d5f1 cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=YnN_nBVA4yaojiBpU0IA:9 a=QEXdDO2ut3YA:10 a=Fk4IpSoW4aLDllm1B1p-:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA0MDAxMiBTYWx0ZWRfX9MZOE6PsTDFc U8tuGxtaoHHMFG6WKWqVzo41YZipMBjUUZd1cdA382NroGuiLoo0/bdKtnMA5I0JPW5sv3y2aFY kYBco7ROEz7Vban/K5iRUP7gffUVFYCnXF0+gFoSTDMjOTtVlFVcz41sK10BNovzNS4bbbTOy6P 2PZJhcpawEiET3vU34nlsKB82u5i9ZYV6xjNlv4RAGy8JXgxmej30zgZJlMm5+3ks/8MaUCwmn1 AyXm8/ahZkmlssdqLk0EJyMbGFMyk4QrcCy/ErNhkEQ1ZJk913GvreYIH2EjKk16u4nIKhzcsAA eRH9FLCCQmnxYpzVQ4xcQCxmR+dQAgH8cZp1bytmcOoWfEzBfHeNiajSIrOtohyiLSbfkqDDV/y LgG7FSqNZkbR7Agd9b5JtRIUaDEAQoyuvTm0nvzLMJTgmMzClbPPMK56x3uzqcQrMDsI331Z8wd 2J0UwiaBaDoA4eR5oQg== X-Proofpoint-ORIG-GUID: QteqWyqYzxaNfZ6wM4zNzlchX9ygtr8k X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-04_01,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 phishscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606040012 Hawi SoC uses QMP phy with version v10.60 for PCIe Gen4 x1. Add the new PCS PCIe specific offsets in a dedicated header file. Signed-off-by: Matthew Leung --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 + .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h | 26 ++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index ba17e53d000f..fb66e2a97ce0 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -41,6 +41,7 @@ #include "phy-qcom-qmp-pcs-pcie-v8.h" #include "phy-qcom-qmp-qserdes-txrx-pcie-v8.h" #include "phy-qcom-qmp-pcs-pcie-v10.h" +#include "phy-qcom-qmp-pcs-pcie-v10_60.h" #define PHY_INIT_COMPLETE_TIMEOUT 10000 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h new file mode 100644 index 000000000000..2df5a45010a4 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V10_60_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V10_60_H_ + +/* Only for QMP V10_60 PHY - PCIE PCS registers */ +#define QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG2 0x00c +#define QPHY_PCIE_V10_60_PCS_TX_RX_CONFIG 0x018 +#define QPHY_PCIE_V10_60_PCS_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_PCIE_V10_60_PCS_OSC_DTCT_ACTIONS 0x090 +#define QPHY_PCIE_V10_60_PCS_EQ_CONFIG1 0x0a0 +#define QPHY_PCIE_V10_60_PCS_G3_RXEQEVAL_TIME 0x0f0 +#define QPHY_PCIE_V10_60_PCS_G4_RXEQEVAL_TIME 0x0f4 +#define QPHY_PCIE_V10_60_PCS_G4_EQ_CONFIG5 0x108 +#define QPHY_PCIE_V10_60_PCS_G4_PRE_GAIN 0x15c +#define QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG1 0x17c +#define QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG3 0x184 +#define QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG5 0x18c +#define QPHY_PCIE_V10_60_PCS_G3_FOM_EQ_CONFIG5 0x1ac +#define QPHY_PCIE_V10_60_PCS_G4_FOM_EQ_CONFIG5 0x1c0 +#define QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG6 0x1d0 + +#endif -- 2.34.1