From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from zg8tmja5ljk3lje4mi4ymjia.icoremail.net (zg8tmja5ljk3lje4mi4ymjia.icoremail.net [209.97.182.222]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C3EE730F803; Fri, 5 Jun 2026 08:23:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.97.182.222 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780647823; cv=none; b=IHwd6T4lJwpCC5OqrfGG0Q0gYd/k6+Pr6RmnOReTdYvulY1NJf4616VQn6GSn0xqqLJt5ZGTtI6ZaBxRAJj8hs9WjRoRfhV3u68+hw/9B19/lFX2IZXzgNstgbTB8p6FTD7M0RfEQFw1NJguHSFzTYqiytIBIBqSzM/TAfQNr8U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780647823; c=relaxed/simple; bh=oyxEFiegdcQoXI3pzVwGCBopEGhO0BpoDHG8Y4dAINM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=KBzXDYK4tDqy2f8GjtYTFpa0gc2/Z3DkQ1EqxnunC6YBJGlL6itvoKVFxJ1CTnyAnsMyS5zSmfNJrstz+/dL29X+wywzN+s7k111upSpAUzUhzxhNtJuND9NRAuCQKwbrDFvalRxk1dHDOQY+DVixYk5QBM8ov8fEoAeP6YbzEY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com; spf=pass smtp.mailfrom=eswincomputing.com; arc=none smtp.client-ip=209.97.182.222 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0005152DT.eswin.cn (unknown [10.12.96.41]) by app2 (Coremail) with SMTP id TQJkCgBHXqF5hyJqVVQiAA--.3400S2; Fri, 05 Jun 2026 16:23:29 +0800 (CST) From: dongxuyang@eswincomputing.com To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ben-linux@fluff.org, ben.dooks@codethink.co.uk, p.zabel@pengutronix.de, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, xuxiang@eswincomputing.com, wangguosheng@eswincomputing.com, pinkesh.vaghela@einfochips.com, Xuyang Dong Subject: [PATCH v7 1/2] dt-bindings: pwm: dwc: Add eswin compatible and resets property Date: Fri, 5 Jun 2026 16:23:18 +0800 Message-Id: <20260605082318.1599-1-dongxuyang@eswincomputing.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20260605082242.1541-1-dongxuyang@eswincomputing.com> References: <20260605082242.1541-1-dongxuyang@eswincomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:TQJkCgBHXqF5hyJqVVQiAA--.3400S2 X-Coremail-Antispam: 1UD129KBjvJXoW7Ww4fWrW8ZFykXw1xurW7Arb_yoW5Jr1UpF W3AFWvqr1fJr17Xw4rJF18CF13Xa95JFW3Gr1Iq3yYk39Fqa1UtFW5Kr15AFW5Ar4IvrW3 Wa93ur13A3Wjvr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBv14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r1q6r43MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l IxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4 A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUBSoAUUUUU= X-CM-SenderInfo: pgrqw5xx1d0w46hv4xpqfrz1xxwl0woofrz/ From: Xuyang Dong EIC7700 use DesignWare IP for PWM controllers. Add ESWIN EIC7700 support in snps,dw-apb-timers-pwm2.yaml. The DesignWare PWM includes separate reset signals dedicated to each clock domain: The presetn signal resets logic in pclk domain. The timer_N_resetn signal resets logic in the timer_N_clk domain. The resets are active-low. The generic snps,dw-apb-timers-pwm2 binding allows one or two optional reset lines depending on SoC integration. On EIC7700, the presetn and timer_N_resetn inputs are physically tied to a single reset line, therefore exactly one reset is required. Signed-off-by: Xuyang Dong --- .../bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 38 +++++++++++++++++-- 1 file changed, 34 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml index 7523a89a1773..a4b7929f2e05 100644 --- a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml @@ -20,12 +20,11 @@ description: instead of having to encode the IP version number in the device tree compatible. -allOf: - - $ref: pwm.yaml# - properties: compatible: - const: snps,dw-apb-timers-pwm2 + enum: + - snps,dw-apb-timers-pwm2 + - eswin,eic7700-pwm reg: maxItems: 1 @@ -43,6 +42,12 @@ properties: - const: bus - const: timer + resets: + minItems: 1 + items: + - description: Interface bus reset + - description: PWM timer logic reset + snps,pwm-number: $ref: /schemas/types.yaml#/definitions/uint32 description: The number of PWM channels configured for this instance @@ -54,6 +59,22 @@ required: - clocks - clock-names +allOf: + - $ref: pwm.yaml# + + - if: + properties: + compatible: + contains: + const: eswin,eic7700-pwm + then: + properties: + resets: + minItems: 1 + maxItems: 1 + required: + - resets + additionalProperties: false examples: @@ -65,3 +86,12 @@ examples: clocks = <&bus>, <&timer>; clock-names = "bus", "timer"; }; + - | + pwm@50818000 { + compatible = "eswin,eic7700-pwm"; + reg = <0x50818000 0x4000>; + #pwm-cells = <3>; + clocks = <&bus>, <&timer>; + clock-names = "bus", "timer"; + resets = <&reset>; + }; -- 2.34.1