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Fri, 05 Jun 2026 10:37:50 +0000 (GMT) Received: from hu-hgautam-hyd.qualcomm.com (hu-hgautam-hyd.qualcomm.com [10.147.247.91]) by APBLRPPMTA01.qualcomm.com (8.18.1.7/8.18.1.7) with ESMTP id 655Abk6l011714; Fri, 5 Jun 2026 10:37:46 GMT From: Harendra Gautam To: Srinivas Kandagatla Cc: Mark Brown , Liam Girdwood , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-sound@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 0/13] ASoC: qcom: Add QAIF driver for Shikra audio platform Date: Fri, 5 Jun 2026 16:07:26 +0530 Message-Id: <20260605103739.3557573-1-harendra.gautam@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-QCInternal: smtphost X-Proofpoint-GUID: csZUSwm1ARqs2xr0vk2W5lZCE4Twi-d_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA1MDEwMyBTYWx0ZWRfX2v4Xa3jrUVOk O5A79pGFkxoF+yAjftgUGP6Uj8siyo/jJhN5pfMialOFi7dRNv72M8ZvVhnhMkSek3/UxFlLa/u /3fnvVXTPT5PyGtQ+Oa2P1cO9WUzOsTBs11hbLTYn5arhFMa+obM1XR+ULW7eXcyMIinKH86drB JsehxrCkbM4U1dXY5Dk6GdkoXjj0327LRgSIag4Nf5ITb5QVtMP5lVoSNjNTeAFp4FlNOHWYmqO YbDzB4AA3D8NhBIuHyQ+NfOStE0X1ipQZeLK6ZoZXenYtUQmmGFkkjTwOmLadPXEvbyhLcZaEbD 6dJT6KtCY/Hk2+zy+5VM0gk6ATgRB7XkxNDLqU0A0DLypKTk0YvsEwl8+MxZM/Hn00XKAoPr3eG rK0NolGKNL12jRYyX4Gm7LMrEuOzLrGcA+qUw3iakfcWK5+zQO5ZAlyXTQCImE9QplWrrUKoKcy ekQK0ZR1T4FseFLE+nQ== X-Authority-Analysis: v=2.4 cv=JNULdcKb c=1 sm=1 tr=0 ts=6a22a6fe cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=qLBaUGd7TCgKCsoal_sA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: csZUSwm1ARqs2xr0vk2W5lZCE4Twi-d_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-05_01,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 spamscore=0 clxscore=1011 adultscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606050103 This series introduces the Qualcomm Audio Interface (QAIF) driver for the Shikra audio platform. Hardware IP Overview ==================== QAIF (Qualcomm Audio Interface) is a fully configurable DMA-based audio subsystem used to transmit and receive audio data over serial audio interfaces (PCM, TDM, MI2S) and to provide a DMA interface for internal codec connections. It manages two independent data paths: Unified Audio Interface (AIF): Serialises and deserialises PCM audio between system memory and external serial audio peripherals. Each interface supports up to 8 independent data lanes, each configurable as TX (speaker) or RX (mic). All lanes of an interface share a single bit clock and frame sync. The AUD_INTFa hardware block controls the serial protocol -- sync source (master/slave), sync mode (short/long PCM, TDM, MI2S), sync delay and inversion, slot and sample widths, active slot masks, lane enable/direction, mono/stereo mode and full-cycle path support for long chip-to-chip connections. Codec DMA Interface (CIF): Provides a parallel DMA interface to the internal Bolero digital codec. The RDDMA path carries playback data to Bolero and the WRDMA path carries capture data from Bolero. Each channel has an INTF_CFG register controlling the active channel enable mask, frame-sync selection, frame-sync delay, frame-sync output gating, dynamic clock gating and 16-bit packing/unpacking. DMA Engine: Read DMAs (RDDMA) fetch audio from DDR/TCM/LPM into a shared on-chip SRAM latency buffer (SHRAM) and drain it to the interface. Write DMAs (WRDMA) collect data from the interface into SHRAM and write it to memory. Each DMA channel owns a private SHRAM region. Two QSB master ports (QXM0 and QXM1) provide the memory fabric. Burst sizes of 1/2/4/8/16 beats and up to 4 outstanding transactions per DMA are supported. Execution Environments (EE): Resources (DMAs, audio interfaces, interface groups) are partitioned among up to 5 EEs via map registers. Each EE receives an independent interrupt output. The interrupt hierarchy has two levels: a summary register identifies the event class (DMA period, underflow/overflow, error response, AUD_INTF underflow/overflow, group done, rate detector, VFR), and per-resource status registers identify the specific channel and event type. Interface Grouping (Bonding): Multiple AIF and CIF interfaces can be bonded into a group to start synchronously and align their DMA period interrupts within half a frame duration using the RDDMA padding feature. Rate Detector: Two rate detector blocks measure the frequency of incoming frame sync or word select signals and generate interrupts on rate change, undetected rate or sync timeout. Block Diagram ============= System Memory (DDR / LPM / TCM) +---------------------------------+ | Circular Buffers (ping-pong) | +----------+----------+-----------+ | ^ 64-bit AXI 64-bit AXI | | +----------v----------+-----------+ | QSB Master Ports | | +----------+ +----------+ | | | QXM0 | | QXM1 | | | +----+-----+ +-----+----+ | +-------|--------------|----------+ | | +-------v--------------v----------+ | Shared RAM (SHRAM) | | +------------+ +------------+ | | | QXM0 Read | | QXM0 Write | | | | SHRAM | | SHRAM | | | +------------+ +------------+ | | +------------+ +------------+ | | | QXM1 Read | | QXM1 Write | | | | SHRAM | | SHRAM | | | +------------+ +------------+ | +---+--------+--------+-------+---+ | | | | +---v--+ +--v---+ +--v---+ +-v----+ |RDDMA | |RDDMA | |WRDMA | |WRDMA | | AIF | | CIF | | AIF | | CIF | |[0..n]| |[0..n]| |[0..n]| |[0..n]| +--+---+ +--+---+ +--+---+ +-+----+ | | ^ ^ | TX | TX | RX | RX v v | | +--+--------------------+ +----+----------+ | Unified Audio Intf | | Codec DMA | | (AIF 0..12) | | Interface | | | | (CIF) | | AUD_INTFa block: | | | | - Serializer (TX) | | RDDMA: DDR -> | | - De-serializer (RX) | | internal | | - Sync gen/detect | | codec | | - Up to 8 data lanes | | WRDMA: codec | | - PCM / TDM / MI2S | | -> DDR | | - Near Pad Logic | | Up to 16 ch | +--+--------------------+ +----+----------+ | Lane 0..7 (TX/RX) | Parallel bus | Bit clk + Frame sync | + Frame sync v v +--+--------+ +------+------+ | External | | Internal | | Serial | | Digital | | Peripherals| | Codec | | (PCM/TDM/ | | (Bolero/ | | MI2S) | | WCD) | +-----------+ +-------------+ Software Design =============== The driver follows the standard ALSA SoC split: qaif-cpu.c: CPU DAI component. Manages clocks, initialises regmap bitfield handles for all DMA and interface control registers, implements DAI ops (startup/shutdown/hw_free/hw_params/trigger) for both AIF and CIF paths, registers an of_xlate_dai_name callback so that sound-dai references using non-sequential DAI IDs resolve correctly, and parses per-interface TDM/MI2S configuration from DT child nodes. qaif-platform.c: PCM platform component. Handles DMA buffer allocation (dma_alloc_pages()), PCM ops (open/close/hw_params/prepare/trigger/ pointer/mmap/copy), two-level IRQ dispatch with period-elapsed notification, and component suspend/resume across power collapse. qaif-shikra.c: Shikra SoC-specific variant descriptor. Provides all register field definitions, DMA-to-DAI index maps, SHRAM geometry, clock names and the DAI driver array. This abstraction keeps the core driver portable across future QAIF integrations. qaif.h / qaif-reg.h: Shared data structures, constants and the complete MMIO register address map consumed by both the CPU and platform drivers. common.c/h: This series also adds asoc_qcom_of_xlate_dai_name(), a shared helper that resolves a sound-dai phandle argument to a DAI name by searching the component DAI driver array by ID. Both lpass-cpu.c and qaif-cpu.c use thin wrappers around this helper, replacing duplicate private implementations. The series is split by functionality to aid review -- register map and data structures first, then CIF ops, AIF ops, probe infrastructure, PCM ops, IRQ handling and finally the Shikra variant glue. Tested on Shikra with 48 kHz stereo MI2S playback and capture over the Audio Interface Zero (AIF0) and Bolero CDC DMA RX/TX paths. Harendra Gautam (13): dt-bindings: sound: Add Qualcomm QAIF DAI ID header dt-bindings: sound: Add Qualcomm QAIF binding MAINTAINERS: Add Qualcomm QAIF driver entry ASoC: qcom: Add QAIF hardware register map ASoC: qcom: Add QAIF shared data structures and variant interface ASoC: qcom: Add QAIF CIF (CDC DMA) DAI ops ASoC: qcom: Add QAIF AIF DAI ops ASoC: qcom: Add generic of_xlate_dai_name helper to common ASoC: qcom: lpass-cpu: Use asoc_qcom_of_xlate_dai_name helper ASoC: qcom: Add QAIF regmap, DT parsing and platform init ASoC: qcom: Add QAIF PCM operations ASoC: qcom: Add QAIF IRQ handling, suspend/resume and platform register ASoC: qcom: Add Shikra QAIF support .../devicetree/bindings/sound/qcom,qaif.yaml | 361 ++++ MAINTAINERS | 10 + include/dt-bindings/sound/qcom,qaif.h | 92 ++ sound/soc/qcom/Kconfig | 11 + sound/soc/qcom/Makefile | 2 + sound/soc/qcom/common.c | 34 + sound/soc/qcom/common.h | 5 + sound/soc/qcom/lpass-cpu.c | 19 +- sound/soc/qcom/qaif-cpu.c | 1586 ++++++++++++++++++++ sound/soc/qcom/qaif-platform.c | 1169 +++++++++++++++ sound/soc/qcom/qaif-reg.h | 405 +++++ sound/soc/qcom/qaif-shikra.c | 585 ++++++++ sound/soc/qcom/qaif.h | 504 +++++++ 13 files changed, 4769 insertions(+), 14 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/qcom,qaif.yaml create mode 100644 include/dt-bindings/sound/qcom,qaif.h create mode 100644 sound/soc/qcom/qaif-cpu.c create mode 100644 sound/soc/qcom/qaif-platform.c create mode 100644 sound/soc/qcom/qaif-reg.h create mode 100644 sound/soc/qcom/qaif-shikra.c create mode 100644 sound/soc/qcom/qaif.h -- 2.34.1