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Peter Anvin" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , Guenter Roeck , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba Subject: [PATCH v2 07/10] x86/msr: Switch rdmsr_safe_on_cpu() users to rdmsrq_safe_on_cpu() Date: Fri, 5 Jun 2026 16:43:11 +0200 Message-ID: <20260605144314.3031049-8-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605144314.3031049-1-jgross@suse.com> References: <20260605144314.3031049-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Flag: NO X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; RCPT_COUNT_TWELVE(0.00)[15]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_HAS_DN(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; TO_DN_SOME(0.00)[]; RCVD_TLS_ALL(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:email,suse.com:mid,imap1.dmz-prg2.suse.org:helo,intel.com:url] X-Spam-Level: X-Spam-Score: -6.80 In order to prepare retiring rdmsr_safe_on_cpu() switch rdmsr_safe_on_cpu() users to rdmsrq_safe_on_cpu(). Signed-off-by: Juergen Gross --- V2: - instead of changing rdmsr_safe_on_cpu(), use rdmsrq_safe_on_cpu() (Ingo Molnar) --- arch/x86/kernel/msr.c | 4 +-- arch/x86/lib/msr-smp.c | 17 +++++++++--- drivers/hwmon/coretemp.c | 32 +++++++++++------------ drivers/hwmon/via-cputemp.c | 16 ++++++------ drivers/thermal/intel/intel_tcc.c | 43 ++++++++++++++++--------------- 5 files changed, 62 insertions(+), 50 deletions(-) diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c index 4469c784eaa0..60334317f30b 100644 --- a/arch/x86/kernel/msr.c +++ b/arch/x86/kernel/msr.c @@ -53,7 +53,7 @@ static ssize_t msr_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) { u32 __user *tmp = (u32 __user *) buf; - u32 data[2]; + u64 data; u32 reg = *ppos; int cpu = iminor(file_inode(file)); int err = 0; @@ -63,7 +63,7 @@ static ssize_t msr_read(struct file *file, char __user *buf, return -EINVAL; /* Invalid chunk size */ for (; count; count -= 8) { - err = rdmsr_safe_on_cpu(cpu, reg, &data[0], &data[1]); + err = rdmsrq_safe_on_cpu(cpu, reg, &data); if (err) break; if (copy_to_user(tmp, &data, 8)) { diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index a434c80408a0..f3c75b681603 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -190,11 +190,22 @@ EXPORT_SYMBOL(wrmsrq_safe_on_cpu); int rdmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) { - u32 low, high; + struct msr_info_completion rv; + call_single_data_t csd; int err; - err = rdmsr_safe_on_cpu(cpu, msr_no, &low, &high); - *q = (u64)high << 32 | low; + INIT_CSD(&csd, __rdmsr_safe_on_cpu, &rv); + + memset(&rv, 0, sizeof(rv)); + init_completion(&rv.done); + rv.msr.msr_no = msr_no; + + err = smp_call_function_single_async(cpu, &csd); + if (!err) { + wait_for_completion(&rv.done); + err = rv.msr.err; + } + *q = rv.msr.reg.q; return err; } diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c index 1259c78c95c6..70711a7cca12 100644 --- a/drivers/hwmon/coretemp.c +++ b/drivers/hwmon/coretemp.c @@ -169,7 +169,7 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) int tjmax_ee = 85000; int usemsr_ee = 1; int err; - u32 eax, edx; + u64 val; int i; u16 devfn = PCI_DEVFN(0, 0); struct pci_dev *host_bridge = pci_get_domain_bus_and_slot(0, 0, devfn); @@ -220,14 +220,14 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) * http://softwarecommunity.intel.com/Wiki/Mobility/720.htm * For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU */ - err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx); + err = rdmsrq_safe_on_cpu(id, 0x17, &val); if (err) { dev_warn(dev, "Unable to access MSR 0x17, assuming desktop" " CPU\n"); usemsr_ee = 0; } else if (c->x86_vfm < INTEL_CORE2_PENRYN && - !(eax & 0x10000000)) { + !(val & 0x10000000)) { /* * Trust bit 28 up to Penryn, I could not find any * documentation on that; if you happen to know @@ -235,8 +235,8 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) */ usemsr_ee = 0; } else { - /* Platform ID bits 52:50 (EDX starts at bit 32) */ - platform_id = (edx >> 18) & 0x7; + /* Platform ID bits 52:50 */ + platform_id = (val >> 50) & 0x7; /* * Mobile Penryn CPU seems to be platform ID 7 or 5 @@ -255,12 +255,12 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) } if (usemsr_ee) { - err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx); + err = rdmsrq_safe_on_cpu(id, 0xee, &val); if (err) { dev_warn(dev, "Unable to access MSR 0xEE, for Tjmax, left" " at default\n"); - } else if (eax & 0x40000000) { + } else if (val & 0x40000000) { tjmax = tjmax_ee; } } else if (tjmax == 100000) { @@ -278,7 +278,7 @@ static int get_tjmax(struct temp_data *tdata, struct device *dev) { struct cpuinfo_x86 *c = &cpu_data(tdata->cpu); int err; - u32 eax, edx; + u64 msrval; u32 val; /* use static tjmax once it is set */ @@ -289,11 +289,11 @@ static int get_tjmax(struct temp_data *tdata, struct device *dev) * A new feature of current Intel(R) processors, the * IA32_TEMPERATURE_TARGET contains the TjMax value */ - err = rdmsr_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); + err = rdmsrq_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &msrval); if (err) { dev_warn_once(dev, "Unable to read TjMax from CPU %u\n", tdata->cpu); } else { - val = (eax >> 16) & 0xff; + val = (msrval >> 16) & 0xff; if (val) return val * 1000; } @@ -314,7 +314,7 @@ static int get_tjmax(struct temp_data *tdata, struct device *dev) static int get_ttarget(struct temp_data *tdata, struct device *dev) { - u32 eax, edx; + u64 val; int tjmax, ttarget_offset, ret; /* @@ -324,14 +324,14 @@ static int get_ttarget(struct temp_data *tdata, struct device *dev) if (tdata->tjmax) return -ENODEV; - ret = rdmsr_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); + ret = rdmsrq_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &val); if (ret) return ret; - tjmax = (eax >> 16) & 0xff; + tjmax = (val >> 16) & 0xff; /* Read the still undocumented bits 8:15 of IA32_TEMPERATURE_TARGET. */ - ttarget_offset = (eax >> 8) & 0xff; + ttarget_offset = (val >> 8) & 0xff; return (tjmax - ttarget_offset) * 1000; } @@ -560,7 +560,7 @@ static int create_core_data(struct platform_device *pdev, unsigned int cpu, struct temp_data *tdata; struct platform_data *pdata = platform_get_drvdata(pdev); struct cpuinfo_x86 *c = &cpu_data(cpu); - u32 eax, edx; + u64 val; int err; if (!housekeeping_cpu(cpu, HK_TYPE_MISC)) @@ -571,7 +571,7 @@ static int create_core_data(struct platform_device *pdev, unsigned int cpu, return -ENOMEM; /* Test if we can access the status register */ - err = rdmsr_safe_on_cpu(cpu, tdata->status_reg, &eax, &edx); + err = rdmsrq_safe_on_cpu(cpu, tdata->status_reg, &val); if (err) goto err; diff --git a/drivers/hwmon/via-cputemp.c b/drivers/hwmon/via-cputemp.c index a5c03ed59c1f..ec421201049d 100644 --- a/drivers/hwmon/via-cputemp.c +++ b/drivers/hwmon/via-cputemp.c @@ -65,28 +65,28 @@ static ssize_t temp_show(struct device *dev, struct device_attribute *devattr, char *buf) { struct via_cputemp_data *data = dev_get_drvdata(dev); - u32 eax, edx; + u64 val; int err; - err = rdmsr_safe_on_cpu(data->id, data->msr_temp, &eax, &edx); + err = rdmsrq_safe_on_cpu(data->id, data->msr_temp, &val); if (err) return -EAGAIN; - return sprintf(buf, "%lu\n", ((unsigned long)eax & 0xffffff) * 1000); + return sprintf(buf, "%lu\n", ((unsigned long)val & 0xffffff) * 1000); } static ssize_t cpu0_vid_show(struct device *dev, struct device_attribute *devattr, char *buf) { struct via_cputemp_data *data = dev_get_drvdata(dev); - u32 eax, edx; + u64 val; int err; - err = rdmsr_safe_on_cpu(data->id, data->msr_vid, &eax, &edx); + err = rdmsrq_safe_on_cpu(data->id, data->msr_vid, &val); if (err) return -EAGAIN; - return sprintf(buf, "%d\n", vid_from_reg(~edx & 0x7f, data->vrm)); + return sprintf(buf, "%d\n", vid_from_reg(~(val >> 32) & 0x7f, data->vrm)); } static SENSOR_DEVICE_ATTR_RO(temp1_input, temp, SHOW_TEMP); @@ -112,7 +112,7 @@ static int via_cputemp_probe(struct platform_device *pdev) struct via_cputemp_data *data; struct cpuinfo_x86 *c = &cpu_data(pdev->id); int err; - u32 eax, edx; + u64 val; data = devm_kzalloc(&pdev->dev, sizeof(struct via_cputemp_data), GFP_KERNEL); @@ -143,7 +143,7 @@ static int via_cputemp_probe(struct platform_device *pdev) } /* test if we can access the TEMPERATURE MSR */ - err = rdmsr_safe_on_cpu(data->id, data->msr_temp, &eax, &edx); + err = rdmsrq_safe_on_cpu(data->id, data->msr_temp, &val); if (err) { dev_err(&pdev->dev, "Unable to access TEMPERATURE MSR, giving up\n"); diff --git a/drivers/thermal/intel/intel_tcc.c b/drivers/thermal/intel/intel_tcc.c index ab61fb122937..c6772a5e073a 100644 --- a/drivers/thermal/intel/intel_tcc.c +++ b/drivers/thermal/intel/intel_tcc.c @@ -181,17 +181,17 @@ static u32 get_temp_mask(bool pkg) */ int intel_tcc_get_tjmax(int cpu) { - u32 low, high; + struct msr msrval; int val, err; if (cpu < 0) - err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msrval.l, &msrval.h); else - err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err = rdmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &msrval.q); if (err) return err; - val = (low >> 16) & 0xff; + val = (msrval.l >> 16) & 0xff; return val ? val : -ENODATA; } @@ -208,17 +208,17 @@ EXPORT_SYMBOL_NS_GPL(intel_tcc_get_tjmax, "INTEL_TCC"); */ int intel_tcc_get_offset(int cpu) { - u32 low, high; + struct msr val; int err; if (cpu < 0) - err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &val.l, &val.h); else - err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err = rdmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &val.q); if (err) return err; - return (low >> 24) & intel_tcc_temp_masks.tcc_offset; + return (val.l >> 24) & intel_tcc_temp_masks.tcc_offset; } EXPORT_SYMBOL_NS_GPL(intel_tcc_get_offset, "INTEL_TCC"); @@ -235,7 +235,7 @@ EXPORT_SYMBOL_NS_GPL(intel_tcc_get_offset, "INTEL_TCC"); int intel_tcc_set_offset(int cpu, int offset) { - u32 low, high; + struct msr val; int err; if (!intel_tcc_temp_masks.tcc_offset) @@ -245,23 +245,23 @@ int intel_tcc_set_offset(int cpu, int offset) return -EINVAL; if (cpu < 0) - err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &val.l, &val.h); else - err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err = rdmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &val.q); if (err) return err; /* MSR Locked */ - if (low & BIT(31)) + if (val.l & BIT(31)) return -EPERM; - low &= ~(intel_tcc_temp_masks.tcc_offset << 24); - low |= offset << 24; + val.l &= ~(intel_tcc_temp_masks.tcc_offset << 24); + val.l |= offset << 24; if (cpu < 0) - return wrmsr_safe(MSR_IA32_TEMPERATURE_TARGET, low, high); + return wrmsr_safe(MSR_IA32_TEMPERATURE_TARGET, val.l, val.h); else - return wrmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, low, high); + return wrmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, val.l, val.h); } EXPORT_SYMBOL_NS_GPL(intel_tcc_set_offset, "INTEL_TCC"); @@ -279,7 +279,8 @@ EXPORT_SYMBOL_NS_GPL(intel_tcc_set_offset, "INTEL_TCC"); int intel_tcc_get_temp(int cpu, int *temp, bool pkg) { u32 msr = pkg ? MSR_IA32_PACKAGE_THERM_STATUS : MSR_IA32_THERM_STATUS; - u32 low, high, mask; + u32 mask; + struct msr val; int tjmax, err; tjmax = intel_tcc_get_tjmax(cpu); @@ -287,19 +288,19 @@ int intel_tcc_get_temp(int cpu, int *temp, bool pkg) return tjmax; if (cpu < 0) - err = rdmsr_safe(msr, &low, &high); + err = rdmsr_safe(msr, &val.l, &val.h); else - err = rdmsr_safe_on_cpu(cpu, msr, &low, &high); + err = rdmsrq_safe_on_cpu(cpu, msr, &val.q); if (err) return err; /* Temperature is beyond the valid thermal sensor range */ - if (!(low & BIT(31))) + if (!(val.l & BIT(31))) return -ENODATA; mask = get_temp_mask(pkg); - *temp = tjmax - ((low >> 16) & mask); + *temp = tjmax - ((val.l >> 16) & mask); return 0; } -- 2.54.0